Array substrate, liquid crystal display, thin film transistor, and manufacturing method of array substrate

1. An array substrate comprising a first thin film transistor and a second thin film transistor on a substrate, wherein

the first thin film transistor includes

a first gate electrode provided on the substrate,

a gate insulating film provided covering the first gate electrode,

a first oxide semiconductor layer and a second oxide semiconductor layer provided on the gate insulating film while overlapping the first gate electrode in plan view, with a first separation portion separating the first oxide semiconductor layer and the second oxide semiconductor layer from each other,

a first source electrode and a first drain electrode provided extending from above the first oxide semiconductor layer and above the second oxide semiconductor layer, respectively, onto the gate insulating film while overlapping the first oxide semiconductor layer or the second oxide semiconductor layer in plan view, with a second separation portion, greater than the first separation portion, separating the first source electrode and the first drain electrode from each other, and

an amorphous silicon layer provided extending on the first separation portion on the gate insulating film, the second separation portion, a part of the first source electrode, and a part of the first drain electrode, and

the second thin film transistor includes

a second gate electrode provided on the substrate,

the gate insulating film provided covering the second gate electrode,

a third oxide semiconductor layer provided on the gate insulating film while overlapping the second gate electrode in plan view, and

a second source electrode and a second drain electrode provided extending from above the third oxide semiconductor layer onto the gate insulating film while overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.

2. The array substrate according to claim 1 , wherein

the first thin film transistor further includes a third source electrode and a third drain electrode provided extending from above the amorphous silicon layer onto the first source electrode and the first drain electrode, respectively, while being separated from each other on the amorphous silicon layer, and

the second thin film transistor further includes

a fourth source electrode provided on the second source electrode, and

a fourth drain electrode provided on the second drain electrode.

3. The array substrate according to claim 2 , wherein

the first thin film transistor further includes a protective insulating film provided covering the amorphous silicon layer, the third source electrode, and the third drain electrode, and

the second thin film transistor further includes the protective insulating film provided covering the third oxide semiconductor layer, the fourth source electrode, and the fourth drain electrode.

4. The array substrate according to claim 2 , wherein

the third drain electrode is provided extending from above the first drain electrode onto the gate insulating film, and

the third drain electrode provided on the gate insulating film is a pixel electrode.

5. The array substrate according to claim 2 , wherein

the first gate electrode and the second gate electrode are formed of a same layer,

the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are formed of a same layer,

the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are formed of a same layer, and

the third source electrode, the third drain electrode, the fourth source electrode, and the fourth drain electrode are formed of a same layer.

6. The array substrate according to claim 2 , wherein

the first gate electrode and the second gate electrode are of a material having a same composition,

the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer are of an oxide semiconductor material having a same composition, and

the third source electrode, the third drain electrode, the fourth source electrode, and the fourth drain electrode are of a material having a same composition.

7. The array substrate according to claim 1 , wherein

the gate insulating film in contact with the amorphous silicon layer is a silicon nitride film, and

the gate insulating film in contact with the third oxide semiconductor layer is a layer stack of a silicon nitride film and a silicon oxide film.

8. The array substrate according to claim 1 , wherein phosphorus is present at an interface of the first oxide semiconductor layer, the second oxide semiconductor layer, the first source electrode, and the first drain electrode to the amorphous silicon layer.

9. The array substrate according to claim 1 , wherein

the first thin film transistor is a transistor for pixel display, and

the second thin film transistor is a transistor for a drive circuit.

10. A liquid crystal display comprising the array substrate according to claim 4 , wherein

the array substrate further includes a slit-shaped counter electrode provided on the gate insulating film while overlapping the pixel electrode in plan view.

11. A thin film transistor comprising:

a substrate;

a gate electrode provided on the substrate;

a gate insulating film provided covering the gate electrode;

a first oxide semiconductor layer and a second oxide semiconductor layer provided on the gate insulating film while overlapping the gate electrode in plan view, with a first separation portion separating the first oxide semiconductor layer and the second oxide semiconductor layer from each other;

a source electrode and a drain electrode provided extending from above the first oxide semiconductor layer and above the second oxide semiconductor layer, respectively, onto the gate insulating film while overlapping the first oxide semiconductor layer or the second oxide semiconductor layer in plan view, with a second separation portion, greater than the first separation portion, separating the source electrode and the drain electrode from each other; and

an amorphous silicon layer provided extending on the first separation portion on the gate insulating film, the second separation portion, a part of the source electrode, and a part of the drain electrode.