Input interface circuit
View Patent ↗An input interface circuit is provided. When a pad voltage is higher than a default operating voltage, a clamping circuit maintains the voltage at a first node at the default operating voltage. A first inverter is coupled between the first node and a second node. A voltage of a third node is adjusted along with the pad voltage (input end of a high-voltage buffering circuit) and the voltage at the second node, and causes the voltage at the third node has a same voltage change trend as the pad voltage. A second inverter is coupled between the third node and a fourth node. A voltage recovery circuit has its input end coupled to the fourth node and its output end coupled to the third node, and selectively couples the third node to a power line or a ground line according to the voltage at the fourth node.
1. An input interface circuit, comprising:
a power line, supplying a default operating voltage;
a ground line, supplying a ground voltage;
an input pad, receiving a pad voltage;
a clamping circuit, coupled between the input pad and a first node, the clamping circuit causing a voltage at the first node to be maintained at the default operating voltage when the pad voltage is higher than the default operating voltage;
a first inverter, having an input end and an output end, the input end coupled to the first node and the output end coupled to a second node;
a high-voltage buffering circuit, having a first input end, a second input end and an output end, the first input end coupled to the input pad, the second input end coupled to the second node, and the output end coupled to a third node, wherein a voltage at the third node is adjusted along with the pad voltage and a voltage at the second node, and the voltage at the third node has a same voltage change trend as the pad voltage;
a second inverter, having an input end and an output end, the input end coupled to the third node and the output end coupled to a fourth node;
a voltage recovery circuit, connected between the power line and the ground line, having an input end and an output end, the input end coupled to the fourth node and the output end coupled to the third node, the third node is selectively coupled to one of the power line and the ground line according to a voltage at the fourth node; and
a third inverter, having an input end thereof coupled to the fourth node and an output end thereof providing a converted voltage.
2. The input interface circuit according to claim 1 , wherein the high-voltage buffering circuit comprises:
a first N-type semiconductor metal-oxide field-effect transistor (MOSFET), having a gate thereof coupled to the second node, a drain thereof coupled to the third node, and a source thereof coupled to the ground line; an
a second N-type MOSFET, having a gate thereof coupled to the input pad, a drain thereof coupled to the power line, and a source thereof and a base thereof coupled to the third node.
3. The input interface circuit according to claim 1 , wherein the voltage recovery circuit comprises:
a third N-type MOSFET, having a gate thereof coupled to the fourth node, a drain thereof coupled to the third node, and a source thereof coupled to the ground line; an
a P-type MOSFET, having a gate thereof coupled to the fourth node, a drain thereof coupled to the third node, and a source thereof coupled to the power line.
4. The input interface circuit according to claim 1 , wherein the voltage recovery circuit comprises:
a P-type MOSFET, having a gate thereof coupled to the fourth node, a drain thereof coupled to the third node, and a source thereof coupled to the power line;
a fourth N-type MOSFET, having a gate thereof coupled to the fourth node, a drain thereof coupled to the third node, and a source thereof coupled to a fifth node;
a fifth N-type MOSFET, having a gate thereof receive a first control signal, a drain thereof coupled to the fifth node, and a source thereof coupled to a ground end;
a sixth N-type MOSFET, having a gate thereof coupled to the fourth node, a drain thereof coupled to the third node, and a source thereof coupled to a sixth node; and
a seventh N-type MOSFET, having a gate thereof receive a second control signal, a drain thereof coupled to the sixth node and a source thereof coupled to the ground end.
5. The input interface circuit according to claim 1 , wherein the first inverter comprises:
a first NOR gate, having a first input end thereof coupled to the first node, a second input end thereof receive a third control signal, and an output end thereof coupled to the second node; and
a second NOR gate, having a first input end thereof coupled to the first node, a second input end thereof receive a fourth signal, and an output end thereof coupled to the second node.
6. The input interface circuit according to claim 1 , wherein a falling threshold of the input interface circuit is associated with a dimension of a transistor in the first inverter.
7. The input interface circuit according to claim 1 , wherein a rising threshold of the input interface circuit is associated with the voltage recovery circuit and a dimension of a transistor in the voltage recovery circuit.