Clocked miller latch design for improved soft error rate
View Patent ↗Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.
1. A circuit, comprising:
a first logic element having an input and an output;
a second logic element having an input coupled to the output of the first logic element and an output coupled to the input of the first logic element;
a capacitor; and
a first transmission gate that selectively connects the capacitor between the output of the first logic element and the output of the second logic element.
2. The circuit of claim 1 , wherein the first and second logic elements are logic inverters.
3. The circuit of claim 1 , wherein the first transmission gate includes a first transistor and a second transistor.
4. The circuit of claim 1 , wherein the first transmission gate couples the capacitor between the output of the first logic element and the output of the second logic element during a hold phase of the circuit.
5. The circuit of claim 4 , wherein a terminal of the capacitor is in a floating state during a write phase of the circuit.
6. The circuit of claim 1 , further comprising a second transmission gate between the output of the second logic element and the input of the first logic element and a third transmission gate coupled to the input of the first logic element.
7. The circuit of claim 6 , wherein the first transmission gate couples the capacitor to the output of the first logic element and the output of the second logic element at a same time the second transmission gate couples the output of the second logic element to the input of the first logic element.
8. The circuit of claim 1 , further comprising a second transmission gate between the output of the second logic element and the input of the first logic element, wherein the first transmission gate selectively connects the capacitor to a connection between the output of the second logic element and an input of the second transmission gate.
9. The circuit of claim 1 , further comprising a second transmission gate between the output of the second logic element and the input of the first logic element, wherein the first transmission gate selectively connects the capacitor to a connection between the output of the second transmission gate and the input of the first logic element.
10. The circuit of claim 1 , wherein the first and second logic elements are part of at least one of a latch circuit or a flip-flop circuit.
11. The circuit of claim 1 , wherein the first and second logic elements are part of a memory circuit.
12. A system having a computing device including a controller, the controller comprising:
a first logic element having an input and an output;
a second logic element having an input coupled to the output of the first logic element and an output coupled to the input of the first logic element;
a capacitor; and
a first transmission gate that selectively connects the capacitor between the output of the first logic element and the output of the second logic element.
13. The system of claim 12 , wherein the first and second logic elements are logic inverters.
14. The system of claim 13 , wherein the first transmission gate connects the capacitor to the output of the first logic element and the output of the second logic element during a hold phase of the controller.
15. The system of claim 14 , wherein a terminal of the capacitor is in a floating state during a write phase of the controller.
16. The system of claim 13 , further comprising a second transmission gate between the output of the second logic inverter and the input of the first logic inverter and a third transmission gate coupled to the input of the first logic inverter.
17. The system of claim 16 , wherein the first transmission gate connects the capacitor to the output of the first logic element and the output of the second logic element at a same time the second transmission gate couples the output of the second logic element to the input of the first logic element.
18. The system of claim 12 , wherein the first and second logic elements are part of a memory.