IP Library Granted Patent US 10,622,469
Granted Patent B2
US 10,622,469 · App. 15/975,938 · Granted Apr 14, 2020

Compound semiconductor device and method for manufacturing the same

Inventors: Junji Kotani (Atsugi, JP); Norikazu Nakamura (Sagamihara, JP)
Assignee: FUJITSU LIMITED
H01L29/7787H01L29/1041H01L29/36H01L29/66462H01L29/0843H01L29/2003H01L29/42316
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Quick Facts
Patent No.
US 10,622,469
App. No.
15/975,938
Granted
Apr 14, 2020
Kind
B2
Abstract

A compound semiconductor device includes an electron transit layer, a spacer layer disposed on the electron transit layer, and an electron supply layer disposed on the spacer layer and containing a donor impurity. The electron supply layer has a concentration distribution of the donor impurity where the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.

Claims (42)

1. A compound semiconductor device, comprising:

a substrate;

an electron transit layer that is disposed over the substrate and in which a two-dimensional electron gas is generated;

a spacer layer disposed on the electron transit layer; and

an electron supply layer disposed on the spacer layer and containing a donor impurity,

the electron supply layer has a concentration distribution of the donor impurity where

the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and

a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.

2. The compound semiconductor device as claimed in claim 1 , wherein

the electron supply layer includes a lower first layer and an upper second layer; and

only the first layer contains the donor impurity.

3. The compound semiconductor device as claimed in claim 2 , wherein the concentration of the donor impurity in the first layer decreases as a distance from the interface increases.

4. The compound semiconductor device as claimed in claim 1 , wherein

the electron supply layer includes a lower first layer and an upper second layer; and

only the first layer contains the donor impurity at a uniform concentration.

5. The compound semiconductor device as claimed in claim 1 , wherein the concentration of the donor impurity in the electron supply layer decreases in a direction from the interface to the upper surface.

6. The compound semiconductor device as claimed in claim 1 , wherein the spacer layer contains the donor impurity with a concentration distribution where a concentration of the donor impurity is at a maximum value at the interface between the electron supply layer and the spacer layer, and the concentration of the donor impurity gradually decreases toward an interface between the electron transit layer and the spacer layer.

7. The compound semiconductor device as claimed in claim 1 , wherein

the first concentration is a maximum value of the concentration distribution; and

the maximum value is within a range between 1×10 18 /cm 3 and 5×10 20 /cm 3 .

8. The compound semiconductor device as claimed in claim 7 , wherein the maximum value is within a range between 5×10 18 /cm 3 and 5×10 19 /cm 3 .

9. The compound semiconductor device as claimed in claim 1 , wherein the donor impurity is one or more elements selected from silicon (Si), germanium (Ge), and oxygen (O).

10. The compound semiconductor device as claimed in claim 1 , further comprising:

an electrode disposed over the electron supply layer; and

an insulation film disposed between the electron supply layer and the electrode.

11. The compound semiconductor device as claimed in claim 1 , further comprising:

an electrode disposed over the electron supply layer,

wherein a portion of the electron supply layer disposed immediately below the electrode does not contain the donor impurity.

12. The compound semiconductor device as claimed in claim 1 , further comprising:

an electrode disposed in a groove that passes through the electron supply layer.

13. A power-supply device, comprising:

a high-voltage circuit including a transistor;

a low-voltage circuit; and

a transformer disposed between the high-voltage circuit and the low-voltage circuit,

the transistor includes

a substrate;

an electron transit layer that is disposed over the substrate and in which a two-dimensional electron gas is generated;

a spacer layer disposed on the electron transit layer; and

an electron supply layer disposed on the spacer layer and containing a donor impurity; and

the electron supply layer has a concentration distribution of the donor impurity where

the donor impurity is at a first concentration at an interface between the electron supply layer and the spacer layer and at a second concentration lower than the first concentration at an upper surface of the electron supply layer, and

a concentration of the donor impurity at one of arbitrarily-selected two positions closer to the upper surface in a thickness direction of the electron supply layer is less than the concentration of the donor impurity at another one of the two positions closer to the interface in the thickness direction.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 10, 2018
From: KOTANI, JUNJI; NAKAMURA, NORIKAZU
To: FUJITSU LIMITED
Reel/Frame 045766/0614 →
Priority Claims (1)
JP 2017-097216 · May 16, 2017 · national
Continuity (1)
Related Publication 20180337271A1 · Nov 22, 2018