IP Library Granted Patent US 10,283,464
Granted Patent B2
US 10,283,464 · App. 16/019,004 · Granted May 7, 2019

Electronic device and manufacturing method of electronic device

Inventor: Daijiro Ishibashi (Yokohama, JP)
Assignee: FUJITSU LIMITED
H01L23/66H01L23/3185H01L23/5226H01L23/5286H01L24/02H01L2223/6627H01L2224/02331H01L2224/02379H01L2224/02381
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Quick Facts
Patent No.
US 10,283,464
App. No.
16/019,004
Granted
May 7, 2019
Kind
B2
Abstract

An electronic device includes a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, a mold resin arranged on a side of the semiconductor device, an insulating layer arranged over the semiconductor device and the mold resin, a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer, a second wiring layer formed over the insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed on a side of an end part of the second grounded layer, a via that couples the first wiring layer and the second area of the second wiring layer, and a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer.

Claims (37)

1. An electronic device comprising:

a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, and a first wiring layer that constitutes a first transmission line that has a predetermined characteristic impedance with the first grounded layer;

a mold resin arranged on a side of the semiconductor device;

an insulating layer arranged over the semiconductor device and the mold resin;

a second grounded layer formed between the semiconductor device and the insulating layer, and the resin mold and the insulating layer;

a second wiring layer formed over the insulating layer and includes

a first area disposed at a part overlapping with the second grounded layer and

a second area disposed on a side of an end part of the second grounded layer, the first area including a first line width and constituting a second transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the second grounded layer, the second area including a second line width smaller than the first line width;

a via that couples the first wiring layer and the second area of the second wiring layer; and

a grounded conductor formed inside the insulating layer at a position overlapping with the second area of the second wiring layer and includes a larger width than the second area in a line width direction of the second area, the grounded conductor extending from the second grounded layer to a position short of the second area along the via,

wherein

the via constitutes a third transmission line that has a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the grounded conductor, and

the second area of the second wiring layer constitutes a fourth transmission line that has a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the grounded conductor.

2. The electronic device according to claim 1 , wherein

the grounded conductor includes

a plurality of columnar parts that each have one end coupled to the second grounded layer and are disposed in the line width direction, and

a coupling conductor that extends in the line width direction and couples the other ends of the plurality of columnar parts.

3. The electronic device according to claim 1 , wherein

the second grounded layer is coupled to the first grounded layer.

4. The electronic device according to claim 1 , wherein

the semiconductor device further includes

a chip insulating layer made on the first surface of the semiconductor chip, and

a protective insulating layer that covers the first wiring layer,

the first grounded layer is made between the semiconductor chip and the chip insulating layer, and

the first wiring layer is disposed to be overlaid on the chip insulating layer.

5. The electronic device according to claim 1 , wherein

the first transmission line, the second transmission line, the third transmission line, and the fourth transmission line are microstrip lines.

6. A manufacturing method of an electronic device, comprising:

stacking a second grounded layer on a semiconductor device including a semiconductor chip, a first grounded layer formed on a surface of the semiconductor chip, and a first wiring layer that constitutes a first transmission line that has a predetermined characteristic impedance with the first grounded layer;

forming a first insulating layer overlaid on the semiconductor device and the second grounded layer;

forming a grounded conductor that has one end coupled to an end part of the second grounded layer and penetrates the first insulating layer in a thickness direction, the grounded conductor including a larger width than the first wiring layer;

forming a second insulating layer overlaid on the first insulating layer;

forming a via that has one end coupled to the first wiring layer and penetrates the first insulating layer and the second insulating layer in the thickness direction, the via extending along the grounded conductor and having the other end that appears outward from the second insulating layer; and

forming a second wiring layer that is overlaid on the second insulating layer and includes a first area disposed at a part overlapping with the second grounded layer and a second area disposed at a position overlapping with the grounded conductor on a side of the end part of the second grounded layer, the first area including a first line width and constituting a second transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the second grounded layer, the second area including a second line width smaller than the first line width and width of the grounded conductor and being coupled to the via,

wherein

the via constitutes a third transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the grounded conductor, and

the second area of the second wiring layer constitutes a fourth transmission line including a predetermined characteristic impedance equal to the characteristic impedance of the first transmission line with the grounded conductor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2018
From: ISHIBASHI, DAIJIRO
To: FUJITSU LIMITED
Reel/Frame 046431/0296 →
Priority Claims (1)
JP 2017-135647 · Jul 11, 2017 · national
Continuity (1)
Related Publication 20190019767A1 · Jan 17, 2019