Level shifting circuit
View Patent ↗A level shifting circuit has an input configured to receive an input signal, wherein the input signal has symmetrical maximum and minimum voltages. The level shifting circuit further includes an output configured to provide an output signal, wherein the output signal has asymmetrical maximum and minimum voltages. The output signal is generated in response to the input signal. The output signal is applied to drive a gate terminal of a SiC MOSFET.
1. A level shifting circuit, comprising:
an input node configured to receive a symmetrical input signal;
an output node configured to output an asymmetrical output signal that is level shifted from the symmetrical input signal by a shift voltage;
a voltage divider circuit connected between the input node and a reference node, the voltage divider circuit having a tap node;
a first diode having an anode coupled to the tap node and a cathode coupled to the second terminal of the capacitor;
wherein the shift voltage is set as a function of a maximum voltage of the symmetrical input signal, a division ratio of the voltage divider and a forward voltage of the first diode; and
a capacitor having a first terminal coupled to the input node and a second terminal coupled to the output node, wherein the capacitor stores the shift voltage.
2. The circuit of claim 1 , further comprising a resistor coupled between the second terminal of the capacitor and the output node.
3. The circuit of claim 1 , wherein the anode of the first diode is connected to the tap node and the cathode of the first diode is connected to the second terminal of the capacitor.
4. The circuit of claim 1 , further comprising a clamping circuit coupled between the output node and the reference node and configured to clamp a voltage of the asymmetrical output signal.
5. The circuit of claim 4 , wherein the gate clamping circuit comprises:
a second diode coupled between the output node and an intermediate node; and
a third diode coupled between the intermediate node and the reference node;
wherein anodes of the first and second diodes are connected to each other.
6. The circuit of claim 1 , further comprising an inductor having a first terminal coupled to the input node and a second terminal coupled to the reference node.
7. The circuit of claim 1 , further comprising a MOS transistor having a gate terminal configured to receive the asymmetrical output signal.
8. The circuit of claim 7 , wherein the reference node is a source terminal of the MOS transistor.
9. The circuit of claim 1 , wherein the reference node is a ground node.
10. The circuit of claim 1 , wherein the symmetrical drive input signal has symmetrical maximum and minimum voltages of +V and −V, respectively, wherein the asymmetrical gate drive signal has asymmetrical maximum and minimum voltages of +V+Vc and −V+Vc, respectively, and wherein Vc is the shift voltage stored across said capacitor.
11. A level shifting circuit configured to provide a voltage shift of Vc and having an input configured to receive an input signal having symmetrical maximum and minimum voltages of +V and −V, respectively, and an output configured to provide an output signal having asymmetrical maximum and minimum voltages of +V+Vc and −V+Vc, respectively.
12. The circuit of claim 11 , wherein the level shifting circuit comprises:
a capacitor coupled between the input and the output;
a voltage divider circuit coupled between the input and a reference node, the voltage divider circuit having a tap node; and
a first diode having an anode coupled to the tap node and a cathode coupled to a terminal of the capacitor.
13. The circuit of claim 12 , wherein a further terminal of the capacitor is connected to the input and said terminal of the capacitor is connected to an intermediate node, and wherein the cathode of the first diode is connected to the intermediate node.
14. The circuit of claim 13 , further comprising a resistor coupled between the intermediate node and the output.
15. The circuit of claim 14 , wherein a first terminal of the resistor is connected to the intermediate node and a second terminal of the resistor is connected to the output.
16. The circuit of claim 12 , wherein the anode of the first diode is connected to the tap node and the cathode of the first diode is connected to the terminal of the capacitor.
17. The circuit of claim 12 , further comprising a clamping circuit coupled between the output and the reference node, said clamping circuit configured to clamp a voltage of the output signal.
18. The circuit of claim 17 , wherein the gate clamping circuit comprises:
a second diode coupled between the output and a further intermediate node; and
a third diode coupled between the further intermediate node and the reference node;
wherein anodes of the first and second diodes are connected to each other.
19. The circuit of claim 12 , wherein Vc is a voltage stored across said capacitor.
20. The circuit of claim 12 , wherein the reference node is a ground node.
21. The circuit of claim 11 , further comprising a MOS transistor having a gate terminal configured to receive the output signal.
22. A circuit, comprising:
an input node configured to receive a symmetrical drive input signal;
a output node configured to output an asymmetrical gate drive signal;
a capacitor having a first terminal directly connected to the input node and a second terminal directly connected to an intermediate node which is coupled to the output node;
a voltage divider circuit comprising first and second resistors coupled in series wherein a terminal of the first resistor is directly connected to the input node and a terminal of the second resistor is directly connected to a reference node, the voltage divider circuit having a tap node; and
a first diode having an anode directly connected to the tap node and a cathode directly connected to the intermediate node.
23. The circuit of claim 22 , further comprising a resistor coupled between the intermediate node and the output node.
24. The circuit of claim 22 , further comprising a clamping circuit coupled between the output node and the reference node and configured to clamp a voltage of the asymmetrical output signal.
25. The circuit of claim 24 , wherein the gate clamping circuit comprises:
a second diode coupled between the output node and an intermediate node; and
a third diode coupled between the intermediate node and the reference node;
wherein anodes of the first and second diodes are connected to each other.
26. The circuit of claim 22 , further comprising an inductor having a first terminal coupled to the input node and a second terminal coupled to the reference node.
27. The circuit of claim 22 , further comprising a MOS transistor having a gate terminal configured to receive the asymmetrical gate drive signal.
28. The circuit of claim 27 , wherein the reference node is a source terminal of the MOS transistor.
29. The circuit of claim 22 , wherein the reference node is a ground node.
30. The circuit of claim 22 , wherein the symmetrical drive input signal has symmetrical maximum and minimum voltages of +V and −V, respectively, wherein the asymmetrical gate drive signal has asymmetrical maximum and minimum voltages of +V+Vc and −V+Vc, respectively, and wherein Vc is a voltage stored across said capacitor.