Direct parity encoder

1. An encoder for wireless local area networking (WLAN) communication, comprising:

a processor configured to divide a generator matrix into a first portion and a second portion, the second portion of the generator matrix including an array of sub-blocks, the array of sub-blocks arranged in rows and columns, each row including M number of sub-blocks and each column including J number of sub-blocks, wherein M and J are integers, each sub-block including Z number of rows and Z number of columns, wherein Z is an integer, a sub-block of the array of sub-blocks including (i) a first set of elements circularly shifted from an identity matrix by a first amount, and (ii) a second set of elements circularly shifted from the identity matrix by a second amount; and

parity bit generation circuitry coupled to the processor, the parity bit generation circuitry configured to generate parity bits according to the array of sub-blocks, the parity bit generation circuitry including:

bit permutation circuitry,

Z number of XOR devices coupled to the bit permutation circuitry,

M sets of storage registers, each set of the M sets of storage registers including Z number of storage registers, each of the Z number of storage registers coupled to a corresponding XOR device of the Z number of XOR devices, and

control circuitry coupled to the bit permutation circuitry and the M sets of storage registers, the control circuitry configured to:

cause the bit permutation circuitry to generate Z number of first bits according to Z number of input bits and the first amount, the Z number of first bits equal to the Z number of input bits when circularly shifted according to the first amount, each of the Z number of first bits provided as input to a corresponding XOR device of the Z number of XOR devices,

cause each storage register of a first set of the M sets of storage registers to store an output of the corresponding XOR device of the Z number of XOR devices,

cause the bit permutation circuitry to generate Z number of second bits according to the Z number of input bits and the second amount, the Z number of second bits equal to the Z number of input bits when circularly shifted according to the second amount, and

cause the Z number of XOR devices to perform bit-wise XOR operations on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, to provide a portion of the parity bits.

2. The encoder of claim 1 , wherein the control circuitry is configured to:

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, while sets of the M sets of storage registers other than the first set do not store the results of the bit-wise XOR operations.

3. The encoder of claim 1 , wherein the control circuitry is configured to:

reset the first set of the M sets of storage registers during a first time period;

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the Z number of outputs from the first set of the M sets of storage registers and the generated Z number of first bits from the bit permutation circuitry during a second time period after the first time period; and

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, during a third time period after the second time period.

4. The encoder of claim 3 , wherein each XOR device of the Z number of XOR devices includes:

a first input port coupled to a corresponding output port of Z number of output ports of the bit permutation circuitry;

a second input port coupled to an output port of a corresponding storage register of the first set; and

an output port coupled to an input port of the corresponding storage register of the first set.

5. The encoder of claim 1 ,

wherein another sub-block of the array of sub-blocks includes a third set of elements circularly shifted from the identity matrix by a third amount and a fourth set of elements circularly shifted from the identity matrix by a fourth amount.

6. The encoder of claim 5 , wherein the parity bit generation circuitry further includes Z number of additional XOR devices coupled to the bit permutation circuitry, wherein the control circuitry is further configured to:

cause the bit permutation circuitry to generate Z number of third bits according to the Z number of input bits and the third amount, the Z number of third bits equal to the Z number of input bits when circularly shifted according to the third amount, each of the Z number of third bits provided as input to a corresponding XOR device of the Z number of additional XOR devices,

cause each storage register of a second set of the M sets of storage registers to store an output of the corresponding XOR device of the Z number of additional XOR devices,

cause the bit permutation circuitry to generate Z number of fourth bits according to the Z number of input bits and the fourth amount, the Z number of fourth bits equal to the Z number of input bits when circularly shifted according to the fourth amount, and

cause the Z number of additional XOR devices to perform bit-wise XOR operations on the stored Z number of outputs from the second set of the M sets of storage registers and the generated Z number of fourth bits from the bit permutation circuitry, to provide another portion of the parity bits.

7. The encoder of claim 6 , wherein the control circuitry is configured to:

cause the second set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the second set of the M sets of storage registers and the generated Z number of fourth bits from the bit permutation circuitry, while sets of the M sets of storage registers other than the second set do not store the results of the additional bit-wise XOR operations.

8. The encoder of claim 6 , wherein the control circuitry is configured to:

reset the first set of the M sets of storage registers and the second set of the M sets of storage registers during a first time period;

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the Z number of outputs from the first set of the M sets of storage registers and the generated Z number of first bits from the bit permutation circuitry during a second time period after the first time period;

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry during a third time period after the second time period;

cause the second set of the M sets of storage registers to store the store results of the bit-wise XOR operations performed on the Z number of outputs from the second set of the M sets of storage registers and the generated Z number of third bits from the bit permutation circuitry during a fourth time period after the third time period; and

cause the second set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the second set of the M sets of storage registers and the generated Z number of fourth bits from the bit permutation circuitry during a fifth time period after the fourth time period.

9. The encoder of claim 1 , wherein the parity bit generation circuitry further includes:

Z number of multiplexers, each multiplexer of the Z number of multiplexers coupled between the corresponding XOR device and a corresponding storage register of the first set; and

Z number of additional multiplexers, each multiplexer of the Z number of additional multiplexers coupled between the corresponding XOR device and a corresponding storage register of a second set of the M sets of storage registers.

10. The encoder of claim 9 , wherein the parity bit generation circuitry further includes:

a feedback multiplexer including:

M number of input ports, each of the M number of input ports coupled to an output port of a corresponding storage register of M number of storage registers, each of the M number of storage registers from a different set of the M sets, and

an output port coupled to an input port of a XOR device of the Z number of XOR devices.

11. The encoder of claim 10 , wherein the control circuitry is configured to:

cause the feedback multiplexer to electrically couple an output port of a storage register of the M number of storage registers to the input port of the XOR device, while a multiplexer of the Z number of multiplexers electrically couples an output port of the XOR device to an input port of the storage register of the M number of storage registers.

12. The encoder of claim 1 , wherein each XOR device of the Z number of XOR devices is a two-input XOR device.

13. The encoder of claim 1 , wherein the first portion of the generator matrix is an identity matrix including J by Z number of rows and J by Z number of columns.

14. An encoder for communication, comprising:

a processor configured to divide a generator matrix into a first portion and a second portion, the second portion of the generator matrix including an array of sub-blocks, the array of sub-blocks arranged in rows and columns, each row including M number of sub-blocks and each column including J number of sub-blocks, each sub-block including Z number of rows and Z number of columns, a sub-block of the array of sub-blocks including (i) a first set of elements circularly shifted from an identity matrix by a first amount, and (ii) a second set of elements circularly shifted from the identity matrix by a second amount; and

parity bit generation circuitry coupled to the processor, the parity bit generation circuitry configured to generate parity bits according to the array of sub-blocks, the parity bit generation circuitry including:

bit permutation circuitry,

Z number of XOR devices coupled to the bit permutation circuitry,

M sets of storage registers, each set of the M sets of storage registers including Z number of storage registers, each of the Z number of storage registers coupled to a corresponding XOR device of the Z number of XOR devices, and

a control circuitry coupled to the bit permutation circuitry and the M sets of storage registers, the control circuitry configured to:

cause the bit permutation circuitry to generate Z number of first bits according to Z number of input bits and the first amount, the Z number of first bits equal to the Z number of input bits when circularly shifted according to the first amount, each of the Z number of first bits provided as input to a corresponding XOR device of the Z number of XOR devices,

cause each storage register of a first set of the M sets of storage registers to store an output of the corresponding XOR device of the Z number of XOR devices,

cause the bit permutation circuitry to generate Z number of second bits according to the Z number of input bits and the second amount, the Z number of second bits equal to the Z number of input bits when circularly shifted according to the second amount, and

cause the Z number of XOR devices to perform bit-wise XOR operations on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, to provide a portion of the parity bits.

15. The encoder of claim 14 , wherein the control circuitry is configured to:

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, while sets of the M sets of storage registers other than the first set do not store the results of the bit-wise XOR operations.

16. The encoder of claim 14 , wherein the control circuitry is configured to:

reset the first set of the M sets of storage registers during a first time period;

cause the first set of the M sets of storage registers to store the Z number of first bits during a second time period after the first time period; and

cause the first set of the M sets of storage registers to store results of the bit-wise XOR operations performed on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry during a third time period after the second time period.

17. The encoder of claim 16 , wherein each XOR device of the Z number of XOR devices includes:

a first input port coupled to a corresponding output port of Z number of output ports of the bit permutation circuitry;

a second input port coupled to an output port of a corresponding storage register of the first set; and

an output port coupled to an input port of the corresponding storage register of the first set.

18. The encoder of claim 14 ,

wherein another sub-block of the array of sub-blocks includes a third set of elements circularly shifted from the identity matrix by a third amount and a fourth set of elements circularly shifted from the identity matrix by a fourth amount.

19. The encoder of claim 18 , wherein the parity bit generation circuitry further includes Z number of additional XOR devices coupled to the bit permutation circuitry, wherein the control circuitry is further configured to:

cause the bit permutation circuitry to generate Z number of third bits according to the Z number of input bits and the third amount, the Z number of third bits equal to the Z number of input bits when circularly shifted according to the third amount, each of the Z number of third bits provided as input to a corresponding XOR device of the Z number of additional XOR devices,

cause each storage register of a second set of the M sets of storage registers to store an output of the corresponding XOR device of the Z number of additional XOR devices,

cause the bit permutation circuitry to generate Z number of fourth bits according to the Z number of input bits and the fourth amount, the Z number of fourth bits equal to the Z number of input bits when circularly shifted according to the fourth amount, and

cause the Z number of additional XOR devices to perform additional bit-wise XOR operations on the stored Z number of outputs from the second set of the M sets of storage registers and the generated Z number of fourth bits from the bit permutation circuitry, to provide another portion of the parity bits.

20. A non-transitory computer readable medium storing instructions when executed by a processor cause the processor to:

divide a generator matrix into a first portion and a second portion, the second portion of the generator matrix including an array of sub-blocks, the array of sub-blocks arranged in rows and columns, each row including M number of sub-blocks and each column including J number of sub-blocks, each sub-block including Z number of rows and Z number of columns, a sub-block of the array of sub-blocks including (i) a first set of elements circularly shifted from an identity matrix by a first amount, and (ii) a second set of elements circularly shifted from the identity matrix by a second amount;

cause a bit permutation circuitry to generate Z number of first bits according to Z number of input bits and the first amount, the Z number of first bits equal to the Z number of input bits when circularly shifted according to the first amount, each of the Z number of first bits provided as input to a corresponding XOR device of Z number of XOR devices;

cause each storage register of a first set of M sets of storage registers to store an output of the corresponding XOR device of the Z number of XOR devices;

cause the bit permutation circuitry to generate Z number of second bits according to the Z number of input bits and the second amount, the Z number of second bits equal to the Z number of input bits when circularly shifted according to the second amount; and

cause the Z number of XOR devices to perform bit-wise XOR operations on the stored Z number of outputs from the first set of the M sets of storage registers and the generated Z number of second bits from the bit permutation circuitry, to provide a portion of parity bits.