Accelerating replication of page tables for multi-socket machines
Described herein is a method for tracking changes made by an application. Embodiments include determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor. Embodiments include adding, by the processor, the cache line to a list of dirty cache lines. Embodiments include, for each respective cache line in the list of dirty cache lines, identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line and updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.
1. A method for tracking changes made by an application, comprising:
determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor;
adding, by the processor, the cache line to a list of dirty cache lines; and
for each respective cache line in the list of dirty cache lines:
identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line; and
updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.
2. The method of claim 1 , further comprising:
determining, by the processor, that the hardware unit has accessed the page table entry of the page table, wherein the page table entry corresponds to the cache line;
adding, by the processor, the cache line to a list of potentially dirty cache lines; and
snooping, by the processor, each respective cache line in the list of potentially dirty cache lines from a respective hardware unit associated with a respective socket of the plurality of sockets that corresponds to the respective cache line; and
determining, by the processor, the write-back in response to the snooping.
3. The method of claim 1 , wherein the page table replica comprises a shadow page table replica that is based on a two-level page table comprising a guest page table associated with a guest system and an extended page table associated with a host system, and wherein the page table on the processor comprises one of:
the guest page table; or
the extended page table.
4. The method of claim 1 , wherein identifying, by the processor, the memory location associated with the socket corresponding to the respective cache line comprises traversing the page table replica to locate the entry.
5. The method of claim 1 , further comprising:
determining, by the processor, a request for a translation lookaside buffer (TLB) flush;
flushing, by the processor, a cache associated with each socket of the plurality of sockets; and
determining, by the processor, the write-back in response to the flushing.
6. The method of claim 1 , wherein identifying, by the processor, the memory location on the socket corresponding to the respective cache line comprises using a pointer stored by the processor to access a circular linked list of page table replicas maintained by an operating system or a hypervisor.
7. The method of claim 1 , wherein the page table in the memory location associated with the processor includes write-through protection, and wherein the write-back is triggered based on the write-through protection.
8. The method of claim 1 , wherein each socket of the plurality of sockets is associated with a respective memory location that stores a respective page table replica, and wherein the processor updates the respective page table replica stored in the respective memory location associated with each socket of the plurality of sockets based on the respective cache line.
9. The method of claim 1 , wherein the processor is a field programmable gate array (FPGA).
10. A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to perform a method for tracking changes made by an application, the method comprising:
determining, by the processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor;
adding, by the processor, the cache line to a list of dirty cache lines; and
for each respective cache line in the list of dirty cache lines:
identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line; and
updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.
11. The non-transitory computer-readable medium of claim 10 , wherein the method further comprises:
determining, by the processor, that the hardware unit has accessed the page table entry of the page table, wherein the page table entry corresponds to the cache line;
adding, by the processor, the cache line to a list of potentially dirty cache lines; and
snooping, by the processor, each respective cache line in the list of potentially dirty cache lines from a respective hardware unit associated with a respective socket of the plurality of sockets that corresponds to the respective cache line; and
determining, by the processor, the write-back in response to the snooping.
12. The non-transitory computer-readable medium of claim 10 , wherein the page table replica comprises a shadow page table replica that is based on a two-level page table comprising a guest page table associated with a guest system and an extended page table associated with a host system, and wherein the page table on the processor comprises one of:
the guest page table; or
the extended page table.
13. The non-transitory computer-readable medium of claim 10 , wherein identifying, by the processor, the memory location associated with the socket corresponding to the respective cache line comprises traversing the page table replica to locate the entry.
14. The non-transitory computer-readable medium of claim 10 , wherein the method further comprises:
determining, by the processor, a request for a translation lookaside buffer (TLB) flush;
flushing, by the processor, a cache associated with each socket of the plurality of sockets; and
determining, by the processor, the write-back in response to the flushing.
15. The non-transitory computer-readable medium of claim 10 , wherein identifying, by the processor, the memory location on the socket corresponding to the respective cache line comprises using a pointer stored by the processor to access a circular linked list of page table replicas maintained by an operating system or a hypervisor.
16. The non-transitory computer-readable medium of claim 10 , wherein the page table in the memory location associated with the processor includes write-through protection, and wherein the write-back is triggered based on the write-through protection.
17. The non-transitory computer-readable medium of claim 10 , wherein each socket of the plurality of sockets is associated with a respective memory location that stores a respective page table replica, and wherein the processor updates the respective page table replica stored in the respective memory location associated with each socket of the plurality of sockets based on the respective cache line.
18. The non-transitory computer-readable medium of claim 10 , wherein the processor is a field programmable gate array (FPGA).
19. A system, comprising: a processor; and a non-transitory computer-readable medium comprising instructions that, when executed by the processor, cause the processor to perform a method for tracking changes made by an application, the method comprising:
determining, by the processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor;
adding, by the processor, the cache line to a list of dirty cache lines; and
for each respective cache line in the list of dirty cache lines:
identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line; and
updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.
20. The system of claim 19 , wherein the method further comprises:
determining, by the processor, that the hardware unit has accessed the page table entry of the page table, wherein the page table entry corresponds to the cache line;
adding, by the processor, the cache line to a list of potentially dirty cache lines; and
snooping, by the processor, each respective cache line in the list of potentially dirty cache lines from a respective hardware unit associated with a respective socket of the plurality of sockets that corresponds to the respective cache line; and
determining, by the processor, the write-back in response to the snooping.