IP Library Granted Patent US 10,839,119
Granted Patent B2
US 10,839,119 · App. 16/262,038 · Granted Nov 17, 2020

Bus wiring searching method and information processing apparatus

Inventor: Yoshitaka Nishio (Yokosuka, JP)
Assignee: FUJITSU LIMITED
G06F30/327
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Quick Facts
Patent No.
US 10,839,119
App. No.
16/262,038
Granted
Nov 17, 2020
Kind
B2
Abstract

An information processing apparatus includes a processor that generates a first node when a bus wiring condition is changed from a first condition to a second condition or when a result of bus wiring is generated based on the first condition. The processor stores the first condition and design data of bus wiring after the change in a storage unit in association with the first node when the bus wiring condition is changed. The processor stores the result of bus wiring, and the design data of bus wiring after the generation in the storage unit in association with the first node when the result of bus wiring is generated, the first condition. The processor searches, upon receiving a designation of a bus wiring condition, for a second node that matches the designated bus wiring condition. The processor outputs design data of bus wiring corresponding to the second node.

Claims (40)

1. A non-transitory computer-readable recording medium having stored therein a program that causes a computer to execute a process, the process comprising:

generating a first node when a bus wiring condition is changed from a first wiring condition to a second wiring condition or when a result of bus wiring is generated based on the first wiring condition;

storing the first wiring condition and design data of bus wiring after the change of the bus wiring condition in a storage unit in association with the first node when the bus wiring condition is changed from the first wiring condition to the second wiring condition;

storing the first wiring condition, the result of bus wiring, and the design data of bus wiring after the result of bus wiring is generated in the storage unit in association with the first node when the result of bus wiring is generated based on the first wiring condition;

searching, upon receiving a designation of a bus wiring condition, for a second node that matches the designated bus wiring condition; and

outputting design data of bus wiring corresponding to the second node.

2. The non-transitory computer-readable recording medium according to claim 1 , the process further comprising:

generating the first node so as to provide a tree structure having a reference node as a root node and the first node as a child node.

3. The non-transitory computer-readable recording medium according to claim 2 , the process further comprising:

calculating a difference between the first wiring condition and a bus wiring condition of each of existing nodes in the tree structure using a breadth-first search from the root node; and

generating the first node under an existing node with a smallest difference.

4. The non-transitory computer-readable recording medium according to claim 3 , the process further comprising:

giving priority to each of a plurality of items when a bus wiring condition has the plurality of items; and

calculating the difference as a value indicating presence/absence of a difference in each of the plurality of items, wherein the value has a higher priority item as a higher order digit.

5. The non-transitory computer-readable recording medium according to claim 4 , the process further comprising:

comparing wiring condition information on a bus, wiring rule information on a wiring rule on a board, and wiring difference information on a wiring difference between a parent node and child nodes; and

calculating a difference for each item between the first node and each of the existing nodes.

6. The non-transitory computer-readable recording medium according to claim 3 , wherein the bus wiring condition includes one or more pieces of information among a bus net definition, a bus wiring target layer, a bus route, a bus automatic wiring priority order, a net line width, and the result of bus wiring.

7. The non-transitory computer-readable recording medium according to claim 2 , the process further comprising:

displaying a tree structure that matches a predetermined search condition; and

receiving the designation of a bus wiring condition by receiving a designation of a node included in the displayed tree structure.

8. The non-transitory computer-readable recording medium according to claim 2 , the process further comprising:

displaying the tree structure;

receiving a designation of two nodes included in the tree structure;

displaying a difference in a bus wiring condition between the two nodes; and

receiving the designation of a bus wiring condition by receiving a designation of one of the two nodes.

9. A bus wiring searching method, comprising:

generating, by a computer, a first node when a bus wiring condition is changed from a first wiring condition to a second wiring condition or when a result of bus wiring is generated based on the first wiring condition;

storing the first wiring condition and design data of bus wiring after the change of the bus wiring condition in a storage unit in association with the first node when the bus wiring condition is changed from the first wiring condition to the second wiring condition;

storing the first wiring condition, the result of bus wiring, and the design data of bus wiring after the result of bus wiring is generated in the storage unit in association with the first node when the result of bus wiring is generated based on the first wiring condition;

searching, upon receiving a designation of a bus wiring condition, for a second node that matches the designated bus wiring condition; and

outputting design data of bus wiring corresponding to the second node.

10. An information processing apparatus, comprising:

a memory; and

a processor coupled to the memory and the processor configured to:

generate a first node when a bus wiring condition is changed from a first wiring condition to a second wiring condition or when a result of bus wiring is generated based on the first wiring condition;

store the first wiring condition and design data of bus wiring after the change of the bus wiring condition in a storage unit in association with the first node when the bus wiring condition is changed from the first wiring condition to the second wiring condition;

store the first wiring condition, the result of bus wiring, and the design data of bus wiring after the result of bus wiring is generated in the storage unit in association with the first node when the result of bus wiring is generated based on the first wiring condition;

search, upon receiving a designation of a bus wiring condition, for a second node that matches the designated bus wiring condition; and

output design data of bus wiring corresponding to the second node.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 30, 2019
From: NISHIO, YOSHITAKA
To: FUJITSU LIMITED
Reel/Frame 048190/0735 →
Priority Claims (1)
JP 2018-026505 · Feb 16, 2018 · national
Continuity (1)
Related Publication 20190258751A1 · Aug 22, 2019