Two-stage IP de-jitter algorithm in a multiplexer for a group of statistically multiplexed single program transport streams
A system and method are provided for encoding and decoding multiplexed video signals to de-jitter the content. A first de-jitter operation is performed on incoming signals and a second de-jitter operation is performed on PCR modified outbound packetized signals after sequencing of the packetized signals has been determined. In one case the second de-jitter operation can be performed using a PLL that is based, at least in part, on the output hardware limitations.
1. A method comprising:
receiving a plurality of input signals each comprising a plurality of packets;
performing a first de jitter operation on each of said plurality of input signals;
determining a sequence for positioning said plurality of packets from each of said plurality of input signals into a multiplexed signal;
determining whether any of said plurality of input signals is to be positioned incorporating a program clock reference;
applying a program clock reference correction to each input signal that is to be positioned incorporation said program clock reference;
performing a second de-jitter operation on each of said input signals to which said program clock reference correction is applied, where said second de-jitter operation is accomplished using a second phase locked loop that is based at least in part on output hardware associated with an output schedule time for said input signals to which said program clock reference has been applied; and
combining said plurality of packets of each of said input signals based at least in part on said sequence for positioning.
2. The method of claim 1 wherein said first de jitter operation modifies an input time stamp.
3. The method of claim 2 wherein said first de jitter operation is accomplished using a first phase locked loop.
4. The method of claim 3 wherein said second de-jitter operation is accomplished using a second phase locked loop.
5. The method of claim 4 wherein said second phase locked loop is based at least in part on output hardware associated with an output schedule time for said input signals to which said program clock reference has been applied.
6. The method of claim 5 wherein said second de-jitter operation modifies said input signal based at least in part on said sequence for positioning.
7. The method of claim 1 wherein said second de-jitter operation modifies said input signal based at least in part on said sequence of packet positioning.
8. The method of claim 7 wherein said first de-jitter operation modifies an input time stamp.
9. A method comprising:
receiving a plurality of input signals each comprising a plurality of packets;
performing a first de-jitter operation on each of said plurality of input signals that modifies an input time stamp and using a first phase locked loop;
determining a sequence for positioning said plurality of packets from each of said plurality of input signals into a multiplexed signal;
determining whether any of said plurality of input signals is to be positioned incorporating a program clock reference;
applying a program clock reference correction to each input signal that is to be positioned incorporation said program clock reference;
performing a second de-jitter operation on each of said input signals to which said program clock reference correction is applied and using a second phase locked loop that is based at least in part on output hardware associated with an output schedule time for said input signals to which said program clock reference has been applied; and
combining said plurality of packets of each of said input signals based at least in part on said sequence for positioning.
10. The method of claim 9 wherein said second de-jitter operation modifies said input signal based at least in part on said sequence for positioning.