Semi-floating gate FET
A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.
1. A device, comprising:
a substrate;
a source in the substrate, the source having a first type of conductivity;
a channel on the source, the channel having the first type of conductivity, the channel having sidewalls extending away from the substrate;
a drain on the channel, the drain having the first type of conductivity;
a terminal on first portions of the sidewalls of the channel, the terminal having a second type of conductivity;
a first gate on the terminal and adjacent to second portions of the sidewalls; and
a second gate on the first gate, first portions of the second gate being spaced from the second portions of the sidewalls by the first gate.
2. The device of claim 1 , further comprising a gate dielectric on the second portions of the sidewalls and positioned between the channel and the first gate.
3. The device of claim 2 wherein the terminal is in direct contact with the first portions of the sidewalls of the channel.
4. The device of claim 1 , wherein the source has sidewalls substantially aligned with the sidewalls of the channel in a first direction.
5. The device of claim 4 , wherein the drain has sidewalls substantially aligned with the sidewalls of the channel in the first direction.
6. The device of claim 5 , further comprising a dielectric layer on the second gate and adjacent to the sidewalls of the drain.
7. The device of claim 6 , wherein the first gate is spaced from the dielectric layer by second portions of the second gate.
8. A device, comprising:
a vertically arranged transistor, including:
a source having sidewalls along a first direction, the source having a first type of conductivity;
a first channel on the source, the first channel having sidewalls that extend along the first direction and are substantially aligned with the sidewalls of the source, the first channel having the first type of conductivity;
a second channel on the first channel, the second channel having sidewalls that extend along the first direction and are substantially aligned with the sidewalls of the first channel, the second channel having the first type of conductivity;
a drain on the second channel, the drain having sidewalls that extend along the first direction and are substantially aligned with the sidewalls of the second channel, the drain having the first type of conductivity;
a first gate on the sidewalls of the first channel;
a second gate on the first gate and on the sidewalls of the second channel; and
a terminal on the sidewalls of the first channel, the terminal having a second type of conductivity.
9. The device of claim 8 wherein the second gate includes a first portion on the first gate and a second portion adjacent to sidewalls of the first gate.
10. The device of claim 9 wherein a first distance between sidewalls of the first gate in the first direction is greater than a second distance between sidewalls of the source in the first direction.
11. The device of claim 8 , wherein the terminal is on first portions of the sidewalls of the first channel, and the first gate is on the terminal.
12. The device of claim 11 , wherein a dielectric layer is on second portions of the sidewalls of the first channel, positioned between the first gate and the first channel.
13. The device of claim 8 , further comprising a dielectric layer adjacent to the sidewalls of the source, the first gate and the second gate being on the dielectric layer.
14. A device, comprising:
a substrate having a first surface;
a source in the substrate, the source having a second surface that is coplanar with the first surface of the substrate, the source having a first type of conductivity;
an intrinsic silicon layer on the second surface of the source;
a first channel on the intrinsic silicon layer, the first channel having the first type of conductivity;
a second channel on the first channel, the second channel having the first type of conductivity;
a drain on the second channel, the drain having the first type of conductivity;
a terminal on a sidewall of the first channel, the terminal having a second type of conductivity;
a first gate on the terminal and adjacent to the first channel and the intrinsic silicon layer; and
a second gate on the first gate.
15. The device of claim 14 , wherein the second gate has first portions on the first gate and second portions on sidewalls of the first gate.
16. The device of claim 15 wherein a first surface of the second gate and a first surface of the second channel are coplanar.
17. The device of claim 1 wherein the channel has a dopant concentration that is lower than a dopant concentration of the source and lower than a dopant concentration of the drain.