Fabricating memory devices with optimized gate oxide thickness
The present disclosure describes apparatuses and methods for manufacturing programmable memory devices with optimized gate oxide thickness. In some aspects, lithography masks are used to fabricate oxide gates for programmable memory devices of an integrated-circuit (IC) die that are thinner than oxide gates fabricated for processor core devices of the IC die. In other aspects, lithography masks are used to fabricate oxide gates for the programmable memory devices of the IC die such that they are thicker than the oxide gates fabricated for the processor core devices of the IC die. By so doing, the programmable memory devices can be manufactured with optimized gate oxide thickness that may reduce programming voltage or increase device reliability of the programmable memory devices.
1. An integrated-circuit (IC) die comprising:
input/output (I/O) devices having oxide gates of a first thickness;
core processor devices having oxide gates of a second thickness, the second thickness of the oxide gates of the core processor devices being different from the first thickness of the oxide gates of the I/O devices; and
non-volatile programmable memory devices having oxide gates of a third thickness, the third thickness of the oxide gates of the non-volatile programmable memory devices being:
(i) thinner than the second thickness of oxide gates of the core processor devices of the IC die; and
(ii) different from the first thickness of oxide gates of the I/O devices of the IC die.
2. The IC die of claim 1 , wherein the non-volatile programmable memory devices are one-time programmable (OTP) memory devices.
3. The IC die of claim 2 , wherein the one-time (OTP) programmable memory devices are configured as electronic anti-fuse memory devices.
4. The IC die of claim 1 , wherein the non-volatile programmable memory devices are multiple-time programmable (MTP) memory devices.
5. The IC die of claim 1 , further comprising a memory device programming circuit configured to program the non-volatile programmable memory devices by altering respective oxide gates of the non-volatile programmable memory devices using a programming voltage.
6. The IC die of claim 5 , wherein the programming voltage used by the memory device programming circuit is approximately twice a voltage at which the processor core devices operate.
7. The IC die of claim 5 , wherein the memory device programming circuit configured to program the non-volatile programmable memory devices programs the non-volatile memory devices based on bit address information or bit value information.
8. The IC die of claim 1 , wherein the oxide gates of the I/O devices, the oxide gates of the core processor devices, or the oxide gates of the non-volatile programmable memory devices are formed with a silicon oxynitride material.
9. The IC die of claim 1 , wherein the oxide gates of the I/O devices, the oxide gates of the core processor devices, or the oxide gates of the non-volatile programmable memory devices are formed with a silicon dioxide material.
10. The IC die of claim 1 , wherein the oxide gates of the I/O devices, the oxide gates of the core processor devices, or the oxide gates of the non-volatile programmable memory devices are formed with a silicon nitride material.
11. The IC die of claim 1 , wherein the oxide gates of the non-volatile programmable memory devices include topographical asperities.
12. A System-on-Chip comprising:
core processor devices having oxide gates of a first thickness;
non-volatile programmable memory devices having oxide gates of a second thickness, the second thickness of the oxide gates of the non-volatile programmable memory devices being thinner than the first thickness of oxide gates of the core processor devices; and
a memory device programming circuit configured to program the non-volatile memory devices by altering respective oxide gates of the non-volatile memory devices using a programming voltage.
13. The System-on-Chip of claim 12 , wherein the non-volatile programmable memory devices of the System-on-Chip are one-time programmable (OTP) memory devices.
14. The System-on-Chip of claim 13 , wherein the OTP programmable memory devices of the System-on-Chip are configured as electronic anti-fuse memory devices.
15. The System-on-Chip of claim 12 , wherein the non-volatile programmable memory devices of the System-on-Chip are multiple-time programmable (MTP) memory devices.
16. The System-on-Chip of claim 12 , further comprising input/output (I/O) devices having oxide gates of a third thickness that is different from the second thickness of the oxide gates of the non-volatile programmable memory devices.
17. The System-on-Chip of claim 12 , wherein the oxide gates of the non-volatile programmable memory devices are formed with one of a silicon oxynitride material, a silicon dioxide material, or a silicon nitride material.
18. A method performed by an integrated-circuit (IC) die, the method comprising:
operating, by a processor of the IC die, processor core devices of the IC die at a first voltage, the processor core devices having oxide gates of a first thickness; and
programming, by a memory device programming circuit of the IC die, non-volatile programmable memory devices of the IC die at a second voltage, wherein:
the non-volatile programmable memory devices have oxide gates of a second thickness that is thinner than the first thickness of the oxide gates of the processor core devices, and
the second voltage for programming the non-volatile programmable memory devices is approximately twice the first voltage at which the processor core devices operate.
19. The method of claim 18 , wherein programming the non-volatile programmable memory devices comprises setting respective bit values of the non-volatile programmable memory devices.
20. The method of claim 18 , further comprising operating input/output (I/O) devices of the IC die, the I/O devices having oxide gates of a third thickness that is different from the second thickness of the oxide gates of the non-volatile programmable memory devices.