Hardware data transport in wireless data transceiver

1. A wireless data transceiver comprising:

a media access controller configured to receive an inbound data packet from an air interface and to buffer the inbound data packet for transport to a host, and to receive an outbound data packet from elsewhere in the wireless data transceiver and to transfer the outbound data packet to the air interface;

a host interface configured to receive the inbound data packet transported from the media access controller and to transfer the inbound data packet to the host, and to receive the outbound data packet from the host for transfer to the media access controller;

transport controller circuitry configured to manage the wireless data transceiver, including generating a management packet and transferring the management packet to the media access controller for transmission, the transport controller circuitry comprising processing circuitry configured to execute instructions, including instructions to perform the transferring of the management packet to the media access controller for transmission; and

hardware data transport circuitry for transporting the inbound data packet from the media access controller to the host interface, and for transporting the outbound data packet from the host interface to the media access controller, without executing instructions to perform the transporting of the inbound data packet or the transporting of the outbound data packet.

2. The wireless data transceiver of claim 1 wherein the transport controller circuitry comprises processing circuitry configured to execute instructions stored in firmware.

3. The wireless data transceiver of claim 2 wherein the processing circuitry is a central processing unit.

4. The wireless data transceiver of claim 2 wherein the processing circuitry is a microprocessor.

5. The wireless data transceiver of claim 2 wherein the processing circuitry is a microcontroller.

6. The wireless data transceiver of claim 1 further comprising:

buffer memory including a plurality of buffer locations configured to store inbound data packets and outbound data packets; and

address memory configured to store a pool of addresses of available buffer locations.

7. The wireless data transceiver of claim 6 wherein:

the hardware data transport circuitry comprises:

a transmit read pointer configured to select an address from the pool of addresses of available buffer locations, and to communicate the selected address to a transmit queue in the media access controller, and

memory circuitry configured to receive the outbound data packet from the host interface and to transfer the outbound data packet to a buffer location indicated by the transmit read pointer;

the media access controller is configured to:

read the outbound data packet from the buffer location as indicated by the selected address in the transmit queue,

transmit the outbound data packet to the air interface, and

release the selected address back to the pool of addresses; and

the hardware data transport circuitry further comprises a transmit write pointer configured to write the released address back into the pool of addresses.

8. The wireless data transceiver of claim 6 wherein:

the hardware data transport circuitry comprises a controller read pointer configured to select an address from the pool of addresses of available buffer locations;

the transport controller circuitry is configured to generate a management data packet for transfer to the air interface via the media access controller, to transfer the outbound data packet to a buffer location indicated by the controller read pointer, and to communicate the selected address to a transmit queue in the media access controller;

the media access controller is configured to:

read the controller data packet from the buffer location as indicated by the selected address in the transmit queue,

transmit the controller data packet to the air interface, and

release the selected address back to the hardware data transport circuitry; and

the hardware data transport circuitry further comprises a transmit write pointer configured to write the released address back into the pool of addresses.

9. The wireless data transceiver of claim 6 wherein:

the media access controller further comprises a receive read pointer configured to, upon receipt of the inbound data packet from the air interface, select at least one address from the pool of addresses;

the media access controller is configured to:

store the inbound data packet in a buffer at the at least one address,

add the at least one address to a receive queue, and

inform the hardware data transport circuitry that the inbound data packet has arrived, and to communicate the at least one address to the hardware data transport circuitry;

the hardware data transport circuitry comprises memory circuitry configured to:

read the inbound data packet from the buffer,

store the inbound data packet, and

forward to inbound data packet to the host interface;

the hardware data transport circuitry is further configured to release the at least one address to the media access controller; and

the media access controller further comprises a receive write pointer configured to write the released at least one address back to the pool of addresses.

10. The wireless data transceiver of claim 9 wherein:

the media access controller is further configured to inform the transport controller circuitry that the inbound data packet has arrived; and

the transport controller circuitry is configured to validate the inbound data packet.

11. The wireless data transceiver of claim 10 wherein:

the transport controller circuitry is configured to determine packet size of the inbound data packet and to inform the host interface of the packet size; and

the host interface is configured to request an amount of data from the hardware data transport circuitry based on the packet size.

12. A method of operating a wireless data transceiver including a media access controller, a host interface, transport controller circuitry and hardware data transport circuitry, the method comprising:

for an outbound management data packet generated at the transport controller circuitry:

at the transport controller circuitry,

executing instructions to transfer the management packet to the media access controller, and

at the media access controller, receiving the outbound management data packet and transferring the outbound data packet to the air interface; and

for an outbound data packet generated at a host:

at the host interface, receiving the outbound data packet for transport to the media access controller and transferring the outbound data packet to the hardware data transport circuitry,

at the hardware data transport circuitry, transporting the outbound data packet from the host interface to the media access controller, without executing instructions to perform the transporting of the outbound data packet, and

at the media access controller, receive an outbound data packet from elsewhere in the wireless data transceiver and transferring the outbound data packet to an air interface.

13. The method of claim 12 wherein the executing instructions comprises executing instructions stored in firmware.

14. The method of claim 12 , further comprising, for an inbound data packet:

at the media access controller, receiving the inbound data packet from an air interface and buffering the inbound data packet for transport to a host;

at the hardware data transport circuitry, transporting the inbound data packet from the media access controller to the host interface, without executing instructions to perform the transporting of the inbound data packet; and

at the host interface, receiving the inbound data packet transported from the media access controller and transferring the inbound data packet to the host.

15. The method of claim 14 further comprising:

storing at least one of inbound data packets and outbound data packets in buffer memory including a plurality of buffer locations; and

storing a pool of addresses of available buffer locations.

16. The method of claim 15 further comprising:

selecting an address from the pool of addresses of available buffer locations, and communicating the selected address to a transmit queue in the media access controller, and

receiving the outbound data packet from the host interface and transferring the outbound data packet to a buffer location indicated by a transmit read pointer;

at the media access controller, reading the outbound data packet from the buffer location as indicated by the selected address in the transmit queue, transmitting the outbound data packet to the air interface, and release the selected address back to the pool of addresses; and

at the hardware data transport circuitry, writing the released address back into the pool of addresses.

17. The method of claim 15 further comprising:

selecting an address from the pool of addresses of available buffer locations, and communicating the selected address to a transmit queue in the media access controller;

at the transport controller circuitry, transferring the outbound management data packet to a buffer location indicated by a controller read pointer;

at the media access controller, reading the outbound management data packet from the buffer location as indicated by the selected address in the transmit queue, transmitting the outbound management data packet to the air interface, and releasing the selected address back to the hardware data transport circuitry; and

at the hardware data transport circuitry, writing the released address back into the pool of addresses.

18. The method of claim 15 further comprising:

at the media access controller, upon receipt of the inbound data packet from the air interface, selecting at least one address from the pool of addresses, storing the inbound data packet in a buffer at the at least one address, adding the at least one address to a receive queue, informing the hardware data transport circuitry that the inbound data packet has arrived, and communicating the at least one address to the hardware data transport circuitry;

at the hardware data transport circuitry, reading the inbound data packet from the buffer, storing the inbound data packet, forwarding the inbound data packet to the host interface, and releasing the at least one address to the media access controller; and

at the media access controller, writing the released at least one address back to the pool of addresses.

19. The method of claim 14 further comprising:

informing the transport controller circuitry that the inbound data packet has arrived; and

validating the inbound data packet at the transport controller circuitry.

20. The method of claim 19 wherein:

the validating comprises determining size of the inbound data packet; the method further comprising:

informing the host interface, by the transport controller circuitry, of the packet size; and

requesting by the host interface, from the hardware data transport circuitry, of an amount of data based on the packet size.