Mid-level instruction cache
A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
1. A circuit, comprising:
a plurality of L1 instruction caches, each of the L1 instruction caches configured to cache instructions for a respective one of a plurality of processors;
a mid-level instruction cache configured to cache instructions for the plurality of processors, the mid-level instruction cache being configured to provide instructions to the plurality of L1 instruction caches, wherein the mid-level instruction cache is configured to prevent the plurality of processors from writing to the mid-level instruction cache; and
a low-level cache configured to 1) provide the instructions to the mid-level instruction cache and 2) maintain a directory indicating locations at which the instructions are stored, the low-level cache being configured to:
a) store an entry to the directory, the entry indicating whether an instruction is stored at the mid-level instruction cache, and
b) prior to deleting the entry, selectively sending an invalidation command to the mid-level instruction cache as a function of whether the instruction is stored at the mid-level instruction cache.
2. The circuit of claim 1 , wherein the entry further indicates one or more of the plurality of L1 instruction caches at which the instruction is stored.
3. The circuit of claim 1 , wherein the entry includes a bit vector, the bit vector including a bit indicating whether the instruction is stored at the mid-level instruction cache.
4. The circuit of claim 1 , further comprising a plurality of L1 data caches, each of the L1 data caches configured to cache data for a respective one of the plurality of processors.
5. The circuit of claim 4 , wherein the directory further indicates locations at which the data are stored.
6. The circuit of claim 1 , wherein the mid-level instruction cache, in response to receiving the invalidation command, is further configured to invalidate a block of the mid-level instruction cache corresponding to the instruction.
7. A method, comprising:
caching instructions for a respective one of a plurality of processors at a plurality of L1 instruction caches;
caching instructions for the plurality of processors at a mid-level instruction cache;
providing instructions to the plurality of L1 instruction caches via the mid-level instruction cache;
providing the instructions to the mid-level instruction cache via a low-level cache;
maintain a directory via the low-level cache indicating locations at which the instructions are stored;
storing an entry to the directory, the entry indicating whether an instruction is stored at the mid-level instruction cache, and
prior to deleting the entry, selectively sending an invalidation command to the mid-level instruction cache as a function of whether the instruction is stored at the mid-level instruction cache; and
preventing the plurality of processors from writing to the mid-level instruction cache.
8. The method of claim 7 , wherein the entry further indicates one or more of the plurality of L1 instruction caches at which the instruction is stored.
9. The method of claim 7 , wherein the entry includes a bit vector, the bit vector including a bit indicating whether the instruction is stored at the mid-level instruction cache.
10. The method of claim 7 , further comprising caching data for a respective one of the plurality of processors at a plurality of L1 data caches.
11. The method of claim 10 , wherein the directory further indicates locations at which the data are stored.
12. The method of claim 7 , further comprising, in response to receiving the invalidation command, invalidating, via the mid-level instruction cache, a block of the mid-level instruction cache corresponding to the instruction.