Metal-oxide semiconductor (MOS) device structure based on a poly-filled trench isolation region
A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.
1. A transistor structure comprising:
a first doped region;
a second doped region extending into the first doped region;
a third doped region extending into the second doped region;
a trench region extending into the first doped region, the second doped region, and the third doped region;
a liner disposed between the trench region and each of the first doped region, the second doped region, and the third doped region; and
a channel region formed in the second doped region, responsive to a voltage applied to the trench region, the channel providing a current path from the first doped region to the third doped region;
wherein the liner has a first surface and a second surface, the first surface in contact with the trench region and wherein the channel region is formed adjacent to the second surface;
multiple horizontal MOS transistor structures or multiple vertical MOS transistor structures adjacent to the same portion of the second surface of the liner that form a cascaded MOS transistor structure; and
wherein the cascaded MOS structure forms one or more electrostatic discharge (ESD) clamps included within a circuit arrangement, wherein the circuit arrangement is disposed between a first ESD clamp of the one or more ESD clamps such that a first terminal of the first ESD clamp is coupled to an input of the circuit arrangement and a first terminal of a second ESD clamp is coupled to an output of the circuit arrangement.
2. The transistor structure of claim 1 , wherein:
the first doped region comprises a first N-type region;
the second doped region comprises a first P-type region extending into the first N-type region;
the third doped region comprises a second N-type region extending into the first P-type region;
the trench region extending into the second N-type region, the first P-type region, and the first N-type region;
the liner disposed between the trench region and each of the second N-type region, the first P-type region, and the first N-type region; and
the channel region formed in the first P-type region, responsive to a voltage applied to the trench region, the channel providing a current path from the second N-type region to the first N-type region.
3. The transistor structure of claim 2 , further comprising:
a first node formed over the trench region;
a second node formed over the second N-type region;
a third node formed over the first P-type region; and
a fourth node formed over the first N-type region.
4. The transistor structure of claim 3 , further comprising:
a fourth doped region comprises a second P-type region extending into the first N-type region; and
a fifth doped region comprises a third N-type region extending into the second P-type region.
5. The transistor structure of claim 4 , further comprising:
a fifth node formed over the first N-type region;
a sixth node formed over second P-type region; and
a seventh node formed over the third N-type region.
6. The transistor structure of claim 5 , wherein the fifth node is coupled to a second source terminal, wherein the sixth node is coupled to a second body terminal, and wherein the seventh node is coupled to a second drain terminal.
7. The transistor structure of claim 6 , wherein the drain of a first MOS transistor is coupled to the source of a second MOS transistor.
8. The transistor structure of claim 6 , wherein the source of a first MOS transistor is coupled to the drain of a second MOS transistor.
9. The transistor structure of claim 4 , wherein multiple channel regions are formed responsive to a gate bias applied to the trench region.
10. The transistor structure of claim 9 , wherein a first channel region is formed in the first P-type region and a second channel region is formed in the second P-type region, wherein the first channel region provides a first current path from the second N-type region to the first N-type region and the second channel region provides a second current path from the first N-type region to the third N-type region.
11. A transistor structure comprising:
a first doped region;
a second doped region extending into the first doped region;
a third doped region extending into the second doped region;
a trench region extending into the first doped region, the second doped region, and the third doped region;
a liner disposed between the trench region and each of the first doped region, the second doped region, and the third doped region; and
a channel region formed in the second doped region, responsive to a voltage applied to the trench region, the channel providing a current path from the first doped region to the third doped region;
wherein the transistor structure comprises an electrostatic discharge (ESD) clamp; and
wherein a source terminal of a first MOS transistor structure is coupled to a drain terminal of a second MOS transistor structure to form a cascaded MOS transistor structure.
12. The transistor structure of claim 11 , wherein:
the first doped region comprises a first N-type region;
the second doped region comprises a first P-type region extending into the first N-type region;
the third doped region comprises a second N-type region extending into the first P-type region;
the trench region extending into the second N-type region, the first P-type region, and the first N-type region;
the liner disposed between the trench region and each of the second N-type region, the first P-type region, and the first N-type region; and
the channel region formed in the first P-type region, responsive to a voltage applied to the trench region, the channel providing a current path from the second N-type region to the first N-type region.
13. The transistor structure of claim 12 , further comprising:
a fourth doped region comprises a second P-type region extending into the first N-type region; and
a fifth doped region comprises a third N-type region extending into the second P-type region.
14. The transistor structure of claim 13 , further comprising:
a first node formed over the trench region;
a second node formed over the second N-type region;
a third node formed over the first P-type region;
a fourth node formed over the first N-type region;
a fifth node formed over the first N-type region;
a sixth node formed over second p-type region; and
a seventh node formed over the third n-type region.
15. The transistor structure of claim 14 , wherein the fifth node is coupled to a second source terminal, wherein the sixth node is coupled to a second body terminal, and wherein the seventh node is coupled to a second drain terminal.
16. The transistor structure of claim 15 , wherein the drain of the first MOS transistor structure is coupled to the source of the second MOS transistor structure.
17. An apparatus comprising:
a first doped region;
a second doped region extending into the first doped region;
a third doped region extending into the second doped region;
a trench region extending into the first doped region, the second doped region, and the third doped region;
a liner disposed between the trench region and each of the first doped region, the second doped region, and the third doped region; and
means for providing a current path from the first doped region to the third doped region;
wherein the liner has a first surface and a second surface, the first surface in contact with the trench region and wherein the means for providing a current path is formed adjacent to the second surface;
means for forming multiple horizontal MOS transistor structures or multiple vertical MOS transistor structures adjacent to the same portion of the second surface of the liner to form cascaded MOS transistor structures; and
wherein the transistor structure comprises an electrostatic discharge (ESD) clamp, and wherein a source terminal of a first MOS transistor structure is coupled to a drain terminal of a second MOS transistor structure to form a cascaded MOS transistor structure.
18. The apparatus of claim 17 , wherein:
the first doped region comprises a first N-type region;
the second doped region comprises a first P-type region extending into the first N-type region;
the third doped region comprises a second N-type region extending into the first P-type region,
the apparatus further comprising:
a fourth doped region comprising a second P-type region extending into a first N-type region;
a fifth doped region comprising a third N-type region extending into the second P-type region; and
means for providing a current path from the third doped region to the fifth doped region.
19. A transistor structure comprising:
a first doped region comprising a first N-type region;
a second doped region comprising a first P-type region extending into the first doped region;
a third doped region comprising a second N-type region extending into the second doped region;
a trench region extending into the first doped region, the second doped region, and the third doped region;
a liner disposed between the trench region and each of the first doped region, the second doped region, and the third doped region; and
a channel region formed in the second doped region, responsive to a voltage applied to the trench region, the channel providing a current path from the first doped region to the third doped region;
wherein the liner has a first surface and a second surface, the first surface in contact with the trench region and wherein the channel region is formed adjacent to the second surface;
multiple horizontal MOS transistor structures or multiple vertical MOS transistor structures adjacent to the same portion of the second surface of the liner that form a cascaded MOS transistor structure;
a first node formed over the trench region;
a second node formed over the second N-type region;
a third node formed over the first P-type region; and
a fourth node formed over the first N-type region.
20. An apparatus comprising:
a first doped region;
a second doped region extending into the first doped region;
a third doped region extending into the second doped region;
a trench region extending into the first doped region, the second doped region, and the third doped region;
a liner disposed between the trench region and each of the first doped region, the second doped region, and the third doped region; and
means for providing a current path from the first doped region to the third doped region; wherein the liner has a first surface and a second surface, the first surface in contact with the trench region and wherein the means for providing a current path is formed adjacent to the second surface; and
means for forming multiple horizontal MOS transistor structures or multiple vertical MOS transistor structures adjacent to the same portion of the second surface of the liner to form cascaded MOS transistor structures;
a fourth doped region comprises a second P-type region extending into a first N-type region;
a fifth doped region comprises a third N-type region extending into the second P-type region; and
means for providing a current path from the third doped region to the fifth doped region.