Multi-stage analog to digital converter
View Patent ↗A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.
1. A multi-stage analog-to-digital converter (ADC), the multi-stage ADC including:
a plurality of ADC stages coupled in a sequence, each ADC stage including:
an asynchronous circuit and a lookup table configured to output a portion of a digital sample representing a level of an input signal in a reference range; and
a level computing circuit configured to generate a next input signal and a next reference range according to the level of the input signal in the reference range, and to transmit the next input signal and the next reference range to a subsequent ADC stage in the sequence; and
a synchronizing and recording circuit configured to receive the portion of the digital sample from each of the plurality of ADC stages, combine the portions by sequentially writing the portions to a location in a memory.
2. The multi-stage ADC according to claim 1 , wherein the portion of the digital sample from each stage has a bit length corresponding to a resolution for each ADC stage; and the digital sample has an overall bit length corresponding to a sum of the bit length of each portion.
3. The multi-stage ADC according to claim 1 , wherein the portion of the digital sample from a first ADC stage in the sequence corresponds includes bits of the digital sample that are more significant than bits included in the portions of the digital sample from subsequent ADC stages in the sequence.
4. The multi-stage ADC according to claim 3 , wherein at least one of the subsequent ADC stages in the sequence is disabled to obtain a faster digitization and lower resolution of the digital sample.
5. The multi-stage ADC according to claim 1 , further comprising an input-output (I/O) communication circuit configured to enable/disable each of the plurality of ADC stages and configured to communicate with an input device coupled to the multi-stage ADC.
6. The multi-stage ADC according to claim 5 , wherein the input device is a sensor configured to output a slow-moving signal.
7. The multi-stage ADC according to claim 5 , wherein all or a portion of the ADC stages are periodically enabled to obtain a digital sample and otherwise disabled to reduce power consumption.
8. The multi-stage ADC according to claim 1 , wherein each ADC stage has a resolution that is different from other ADC stages in the plurality of ADC stages.
9. The multi-stage ADC according to claim 1 wherein the plurality of ADC stages are current-mode ADC stages.
10. An analog-to-digital converter (ADC) stage for a multi-stage ADC, the ADC stage comprising:
a front-end computing circuit configured to receive an input signal and a reference range, and to output signals at a plurality of front-end outputs, each front-end output corresponding to a comparison between the input signal and a level in the reference range;
an encoding circuit that receives the plurality of outputs and, based on the plurality of outputs, retrieves a digital word from a lookup table and outputs the digital word at an ADC-stage output; and
a quantum-level computing circuit coupled to the input signal and to the plurality of front-end outputs, the quantum-level computing circuit configured to determine a relative level of the input signal within the reference range and to modify, based on the relative level, the reference range and the input signal for a subsequent ADC stage in the multi-stage ADC.
11. The ADC stage according to claim 10 , wherein the front-end computing circuit is an asynchronous, analog circuit.
12. The ADC stage according to claim 10 , wherein the ADC stage is a voltage-mode ADC and the input signal is a voltage.
13. The ADC stage according to claim 10 , wherein the ADC stage is a current-mode ADC and the input signal is a current.
14. The ADC stage according to claim 10 , wherein each signal at each of the plurality of front-end outputs is a voltage corresponding to a high level or a low level, the voltage generated by a comparator.
15. The ADC stage according to claim 14 , wherein the encoding circuit includes a decision block that includes a plurality of decision-block inputs that are coupled to the plurality of front-end outputs and that further includes a plurality of decision-block outputs that are coupled to a plurality of lookup-table inputs, the decision-block configured to:
output a high-level voltage at one of the decision-block outputs based on a combination of high level and low level voltages at the decision-block inputs.
16. The ADC stage according to claim 15 , wherein the lookup table is configured to store a plurality of digital words, each digital word corresponding to one of the plurality of lookup-table inputs, so that a high-level voltage at one of the lookup table inputs configures the lookup table to retrieve the digital word from the lookup table and output the digital word at the ADC-stage output.
17. The ADC stage according to claim 10 , wherein the lookup table includes a memory and the ADC-stage output is a digital signal generated to correspond to an entry in the memory.
18. The ADC stage according to claim 17 , wherein generating the ADC-stage output does not include combinatorial or sequential logic.
19. A method for digitizing an analog signal, comprising:
receiving an input signal and a reference range at an ADC stage in a sequence of ADC stages;
comparing the input signal to a plurality of levels in the reference range;
identifying an entry in a lookup table based on the comparison of the input signal to the plurality of levels;
generating a portion of a digital sample representing the input signal based on the entry;
determining a level of the input signal within the reference range;
modifying the input signal and the reference range; and
repeating the receiving, comparing, identifying, generating, determining, and modifying at a subsequent ADC stage in the sequence of ADC stages.
20. The method for digitizing an analog signal according to claim 19 , further comprising:
appending the portions generated at each ADC stage in the sequence of ADC stages to form the sample of the input signal.