IP Library Granted Patent US 10,771,281
Granted Patent B1
US 10,771,281 · App. 16/673,607 · Granted Sep 8, 2020

Semi-differential signaling for DSI3 bus enhancement

Inventors: Tomas Suchy (Brno, CZ); Lukas Vykydal (Olomouc, CZ); Pavel Hartl (Brno, CZ); Marek Hustava (Bratislava, SK)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04L12/40045H04L25/0272H04L2012/40273
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,771,281
App. No.
16/673,607
Granted
Sep 8, 2020
Kind
B1
Abstract

A semi-differential signaling technique as well as bus devices and communication systems that exploit this technique to enhance the performance of the DSI3 bus. In one embodiment, there is provided a DSI3 master device that can be coupled to a DSI3 slave device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor. The master device includes: a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor to supply power to the slave device; a signal node that connects to the signal conductor; and a driver that drives the signal node relative to a reference voltage midway between voltages of the power supply node and the power return node.

Claims (31)

1. A master device that couples to a slave device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor, the master device comprising:

a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor to supply power to the slave device;

a signal node that connects to the signal conductor; and

a driver that drives the signal node relative to a reference voltage midway between voltages of the power supply node and the power return node.

2. The master device of claim 1 , wherein the driver is part of a transceiver that maintains physical compatibility with the DSI3 (3rd generation distributed system interface) standard while supporting semi-differential signaling when employed in conjunction with a compatible slave device.

3. The master device of claim 1 , further comprising a voltage divider that derives the reference voltage from the voltages of the power supply node and the power return node.

4. A slave device that couples to a master device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor, the slave device comprising:

a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor to receive power from the master device;

a signal node that connects to the signal conductor; and

a receiver that senses a voltage of the signal node relative to a reference voltage midway between voltages of the power supply node and the power return node.

5. The slave device of claim 4 , wherein the receiver is part of a transceiver that maintains physical compatibility with the DSI3 (3rd generation distributed system interface) standard while supporting semi-differential signaling when employed in conjunction with a compatible master device.

6. The slave device of claim 4 , further comprising a voltage divider that derives the reference voltage from the voltages of the power supply node and the power return node.

7. The slave device of claim 6 , wherein the receiver includes an analog-to-digital converter that uses the reference voltage as a zero point.

8. The slave device of claim 6 , wherein the receiver includes a differential amplifier having the reference voltage and the voltage of the signal node coupled to its inputs.

9. The slave device of claim 4 , wherein the receiver includes a differential amplifier with an impedance configuration that offsets the sensed signal node voltage by half a voltage of the power supply node.

10. A communication system comprising:

a slave device; and

a master device coupled to the slave device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor, the master device comprising:

a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor;

a signal node that connects to the signal conductor; and

a driver that drives the signal node relative to a reference voltage midway between voltages of the master device's power supply node and the master device's power return node;

the slave device comprising:

a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor;

a signal node that connects to the signal conductor; and

a receiver that senses a voltage of the signal node relative to a reference voltage midway between voltages of the slave device's power supply node and the slave device's power return node.

11. The communication system of claim 10 , wherein the power return conductor connects to ground at no more than one point to ensure current flow via the power supply conductor returns via the power return conductor.

12. A semi-differential signaling method that comprises:

supplying power to a slave device via current flow through a power supply conductor and a power return conductor; and

driving a voltage of a signal conductor relative to a reference voltage midway between voltages of the power supply conductor and the power return conductor, said driving operating to communicate data to the slave device.

13. The method of claim 12 , further comprising: deriving a reference voltage midway between voltages of a power supply terminal and a power return terminal, the power supply terminal being connected to the power supply conductor and the power return terminal being connected to the power return conductor.

14. The method of claim 13 , wherein said deriving employs a voltage divider coupled between the power supply terminal and the power return terminal.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2019
From: SUCHY, TOMAS; VYKYDAL, LUKAS; HARTL, PAVEL; HUSTAVA, MAREK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 050909/0748 →