Electrostatic discharge handling for sense IGBT using Zener diode
View Patent ↗A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.
1. A semiconductor transistor device, comprising:
a main Insulated Gate Bipolar Transistor (IGBT) having a main gate, a main collector, and a main emitter;
a sense IGBT having a sense gate, a sense collector, and a sense emitter, the sense gate being electrically connected to the main gate, and the sense collector being electrically connected to the main collector;
a sense resistor connected between the sense emitter and the main emitter; and
back-to-back Zener diodes connected between the sense gate and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event,
wherein the main emitter includes a main emitter region formed on a substrate, and isolated by a first junction termination extension (JTE),
a sense emitter region is formed in an epitaxial layer and isolated by a second JTE formed in a first ring formation surrounding the sense emitter region, the epitaxial layer including an electrically isolated area between the first JTE and the second JTE, and
the back-to-back Zener diodes are formed in a second ring formation on a polysilicon layer that is formed on an insulating layer above a portion of at least the second JTE.
2. The semiconductor transistor device of claim 1 , wherein the back-to-back Zener diodes are formed using alternating n-doped and p-doped regions connected between a gate contact of the sense gate and a sense emitter contact of the sense emitter.
3. The semiconductor transistor device of claim 2 , wherein the alternating n-doped and p-doped regions includes at least two n-doped regions and at least two p-doped regions.
4. The semiconductor transistor device of claim 1 , further comprising:
a first plurality of gate trenches formed in the main emitter region and forming at least a portion of the main gate.
5. The semiconductor transistor device of claim 4 , further comprising:
a second plurality of gate trenches formed in the sense emitter region and forming at least a portion of the sense gate.
6. The semiconductor transistor device of claim 1 , wherein the second ring formation at least partially surrounds a sense contact of the sense emitter and is at least partially surrounded by a gate contact connecting the sense gate and the main gate.
7. The semiconductor transistor device of claim 1 , wherein a sense current through the sense resistor is proportional to a main current through the main emitter.
8. A semiconductor transistor device, comprising:
a substrate;
a main emitter region formed on the substrate and isolated by a first junction termination extension (JTE), the main emitter region forming a main emitter of a main Insulated Gate Bipolar Transistor (IGBT);
a first plurality of gate trenches formed in the main emitter region and forming a main gate of the main IGBT;
a sense emitter region formed in an epitaxial layer and isolated by a second JTE, the sense emitter region forming a sense emitter of a sense IGBT;
a second plurality of gate trenches formed in the sense emitter region and forming a sense gate of the sense IGBT, and electrically connected to the main gate of the main IGBT; and
a polysilicon layer having alternating n-doped and p-doped regions forming back-to-back Zener diodes, and connected between a gate contact common to the main gate and the sense gate, and a sense emitter contact of the sense emitter,
wherein the sense emitter region is isolated by the second JTE being formed in a first ring formation surrounding the sense emitter region, and the epitaxial layer includes an electrically isolated area between the first JTE and the second JTE, and
the back-to-back Zener diodes are formed in a second ring formation on a polysilicon layer that is formed on an insulating layer above at least a portion of the second JTE.
9. The semiconductor transistor device of claim 8 , wherein the alternating n-doped and p-doped regions includes at least two n-doped regions and at least two p-doped regions.
10. The semiconductor transistor device of claim 8 , wherein the sense IGBT is configured to provide current sensing of a current flow through the main IGBT.
11. The semiconductor transistor device of claim 10 , wherein the current sensing is provided using a sense resistor connected between the main emitter and the sense emitter.