IP Library Granted Patent US 11,445,137
Granted Patent B2
US 11,445,137 · App. 16/683,977 · Granted Sep 13, 2022

Systems and methods for reference settling

Inventor: Rajashekar Benjaram (Bangalore, IN)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04N5/37455H03M1/466H03M1/66H04N5/378
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Quick Facts
Patent No.
US 11,445,137
App. No.
16/683,977
Granted
Sep 13, 2022
Kind
B2
Abstract

An imaging system may include an image sensor. The image sensor may have an array of image pixels arranged in rows and columns. Each column of image pixels may be coupled to column readout circuitry via a corresponding column line. The column readout circuitry may include analog-to-digital conversion circuitry. The analog-to-digital conversion circuitry may include split MSB and LSB capacitor banks. The MSB capacitor bank may include capacitors selectively coupled to a coarse reference voltage or a fine reference voltage. The LSB capacitor bank may include capacitors electively coupled to the coarse reference voltage.

Claims (11)

1. Digital-to-analog conversion circuitry that receives an input signal, the digital-to-analog conversion circuitry comprising:

a first plurality of capacitors associated with a first capacitor bank, wherein each capacitor in the first plurality of capacitors is configured to sample the input signal at a first terminal and to receive a selected one of a coarse reference voltage, a fine reference voltage, and an additional reference voltage at a second terminal, and wherein the first terminal of a given capacitor in the first plurality of capacitors is configured to receive an input voltage of the input signal using a sampling switch, and the second terminal of the given capacitor in the first plurality of capacitors is configured to selectively receive the coarse reference voltage using first and second switches and to selectively receive the fine reference voltage using the first switch and a third switch; and

a second plurality of capacitors associated with a second capacitor bank, wherein each capacitor in the second plurality of capacitors is configured to sample the input signal at a first terminal and to receive a selected one of the coarse reference voltage and the additional reference voltage at a second terminal.

2. The digital-to-analog conversion circuitry defined in claim 1 , wherein the additional reference voltage is a ground voltage.

3. The digital-to-analog conversion circuitry defined in claim 1 , wherein the coarse reference voltage and the fine reference voltage are voltages larger than a ground voltage.

4. The digital-to-analog conversion circuitry defined in claim 1 , wherein the coarse reference voltage and the fine reference voltage are generated based on a same initial reference voltage.

5. The digital-to-analog conversion circuitry defined in claim 1 , wherein the second terminal of the given capacitor in the first plurality of capacitors is configured to receive the additional reference voltage using a fourth switch.

6. The digital-to-analog conversion circuitry defined in claim 5 , wherein the second terminal of a given capacitor in the second plurality of capacitors is configured to receive the coarse reference voltage using a fifth switch and the second terminal of the given capacitor in the second plurality of capacitors is configured to receive the additional reference voltage using a sixth switch.

7. The digital-to-analog conversion circuitry defined in claim 1 , further comprising:

an additional capacitor having first and second terminals, wherein the first terminal of the additional capacitor is coupled to the first capacitor bank, and the second terminal of the additional capacitor is coupled to the second capacitor bank.

8. The digital-to-analog conversion circuitry defined in claim 7 , wherein the sampling switch is coupled to the first terminal of the additional capacitor, and the first terminal of the additional capacitor is configured to provide an output voltage for the digital-to-analog conversion circuitry.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2019
From: BENJARAM, RAJASHEKAR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051011/0513 →
Priority Claims (1)
IN 201911028735 · Jul 17, 2019 · national
Continuity (1)
Related Publication 20210021781A1 · Jan 21, 2021