IP Library Granted Patent US 11,386,027
Granted Patent B2
US 11,386,027 · App. 16/697,361 · Granted Jul 12, 2022

Network switch with endpoint and direct memory access controllers for in-vehicle data transfers

Inventors: Manfred Kunz (Rastatt, DE); Markus Althoff (Achern, DE); Xiongzhi Ning (Karlsruhe, DE)
Assignee: Marvell Asia Pte, Ltd.
G06F13/28G06F9/30098G06F9/4411G06F9/544G06F13/4022
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Quick Facts
Patent No.
US 11,386,027
App. No.
16/697,361
Granted
Jul 12, 2022
Kind
B2
Abstract

A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Claims (61)

1. A network switch comprising:

a data bus;

a register;

an endpoint controller configured to receive a descriptor generated by a device driver of a host system and transmitted from the host system to the network switch, to store the descriptor in the register, and to transfer data between a root complex controller of the host system and the data bus, wherein the descriptor identifies an address of a buffer in a memory of the host system and the host system is separate from the network switch; and

a direct memory access controller configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver and independently of at least one of the device driver or a host controller of the host system, to control transfer of the data between (i) the memory of the host system and (ii) a network device separate from the network switch and the host system, wherein the direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

2. The network switch of claim 1 , wherein the endpoint controller is a peripheral component interconnect express device transferring the data according to a peripheral component interconnect express protocol.

3. The network switch of claim 1 , wherein the indication is a flag stored in the memory, an interrupt, or a signal.

4. The network switch of claim 1 , further comprising:

a medium access control device configured to transfer the data to or from the direct memory access controller; and

an Ethernet switch configured to transfer the data between the medium access control device and the network device connected to the network switch.

5. The network switch of claim 1 , wherein the network device is a sensor, an actuator, a peripheral component interconnect express device, or an endpoint device.

6. The network switch of claim 1 , further comprising a medium access control device, wherein, while independently controlling transfer of the data, the direct memory access controller is configured to transfer the data between the data bus and the medium access control device without interaction with the host controller of the host system.

7. The network switch of claim 1 , wherein the direct memory access controller is configured to obtain control of the buffer of the memory from the device driver prior to transfer of the data and, after transferring the data, to generate an interrupt to return control of the buffer to the device driver.

8. The network switch of claim 1 , further comprising another controller configured to, receive a rule stored in the memory and, based on the rule, to inspect a frame received from the network device at the network switch and to either drop the frame or forward the frame to the device driver, an application controller of the host system or a denial of service controller of the host system.

9. A data transfer system comprising:

the network switch of claim 1 ;

the memory;

the host controller implementing the device driver; and

the root complex controller configured to provide the host controller and the direct memory access controller access to the memory.

10. The data transfer system of claim 9 , wherein:

the device driver is configured to transfer control of the buffer to the direct memory access controller; and

the direct memory access controller is configured to return control of the buffer back to the device driver.

11. The data transfer system of claim 9 , wherein the root complex controller is configured to control transfer of control information between the device driver and the memory.

12. The data transfer system of claim 9 , wherein the root complex controller and the endpoint controller are peripheral component interconnect express devices operating according to a peripheral component interconnect express protocol.

13. The data transfer system of claim 9 , further comprising a denial of service controller configured to receive a frame from the network switch, to determine whether the frame is likely associated with an attack, to change a rule stored in the memory and to send the changed rule to the network switch to drop another frame or a connection with the network device.

14. A method of operating a network switch, the method comprising:

receiving at an endpoint controller of the network switch a descriptor generated by a device driver of a host system and transmitted from the host system to the network switch, wherein the descriptor identifies an address of a buffer in a memory of the host system and the host system is separate from the network switch;

storing the descriptor in a register;

transferring data between a root complex controller of the host system and a data bus of the network switch;

receiving at a direct memory access controller the address of the buffer from the endpoint controller or the register, wherein the direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller; and

based on the address and an indication generated by the device driver and independently of at least one of the device driver or a host controller of the host system, controlling transfer of the data between (i) the memory of the host system and (ii) a network device separate from the network switch and the host system.

15. The method of claim 14 , further comprising transferring the data according to a peripheral component interconnect express protocol via the endpoint controller.

16. The method of claim 14 , further comprising:

transferring the data to or from the direct memory access controller via a medium access control device; and

transferring the data between the medium access control device and the network device connected to the network switch via an Ethernet switch.

17. The method of claim 14 , further comprising, while independently controlling transfer of the data, transferring via the direct memory access controller the data between the data bus and a medium access control device without interaction with the host controller of the host system.

18. The method of claim 14 , further comprising:

obtaining at the direct memory access controller control of the buffer of the memory from the device driver prior to transfer of the data; and

after transferring the data, generating an interrupt to return control of the buffer to the device driver.

19. The method of claim 14 , further comprising:

receiving a rule stored in the memory; and

based on the rule, inspecting a frame received from the network device at the network switch and either drop the frame, forward the frame to the device driver, an application controller of the host system or a denial of service controller of the host system.

20. The method of claim 14 , further comprising:

receiving a frame from the network switch;

determining whether the frame is likely associated with an attack;

changing a rule stored in the memory; and

sending the changed rule to the network switch to drop another frame or a connection with the network device.

21. The network switch of claim 1 , wherein the direct memory access controller of the network switch is configured, based on the received address, to access the buffer and to transfer the data between the host system and the network device independent of the device driver and the host controller of the host system.

22. The network switch of claim 1 , wherein the network switch is configured as a peripheral component interconnect express endpoint relative to the host controller of the host system and controlled by the host controller using peripheral component interconnect express protocols and a peripheral component interconnect express link.

23. The network switch of claim 22 , wherein operations of the direct memory access controller are controlled by the host controller via the endpoint controller.

24. The network switch of claim 22 , further comprising a memory, wherein:

the direct memory access controller is granted control of the buffer by the host controller; and

the memory operates based on a rule received from the host controller.

25. The network switch of claim 1 , further comprising a memory configured to:

receive a rule from the host controller of the host system;

inspect a frame received from the network device; and

based on the rule and the inspection of the frame, at least one of

preventing direct memory access storage of the frame in the memory of the host system, or

instead of sending the frame to the memory of the host system, redirecting the frame to one of the device driver, an application controller and a denial of service controller.

26. The network switch of claim 1 , wherein the endpoint controller is configured to allow the network switch to operate as an endpoint device relative to the host system by communicating with the root complex controller of the host system and controlling operation of the network switch including reception of the descriptor and transfer of the data between the root complex controller and the data bus.

27. The network switch of claim 1 , wherein the direct memory access controller is configured, based on the address and an indication generated by the device driver, to grant control of the buffer of the host system to the network switch.

Assignments (7)
MERGER Recorded Sep 5, 2025
From: INFINEON TECHNOLOGIES US NEWCO LLC
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 072563/0971 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2025
From: MARVELL ASIA PTE LTD
To: INFINEON TECHNOLOGIES US NEWCO LLC
Reel/Frame 072558/0700 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2021
From: MARVELL ASIA PTE, LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 056287/0377 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2021
From: MARVELL WORLD TRADE LTD.
To: MARVELL ASIA PTE, LTD.
Reel/Frame 056287/0580 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2021
From: ALTHOFF, MARKUS; NING, XIONGZHI
To: MARVELL SEMICONDUCTOR GERMANY GMBH
Reel/Frame 056232/0248 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2021
From: MARVELL SEMICONDUCTOR GERMANY GMBH
To: MARVELL ASIA PTE, LTD.
Reel/Frame 056232/0324 →
EMPLOYMENT AGREEMENT Recorded Nov 4, 2020
From: KUNZ, MANFRED
To: MARVELL SEMICONDUCTOR GERMANY GMBH
Reel/Frame 056213/0410 →
Continuity (2)
Provisional Application 62772506 · Nov 28, 2018
Related Publication 20200167300A1 · May 28, 2020