Electrostatic discharge protection
In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.
1. An electronic device comprising:
a substrate having one of a p-type doping or an n-type doping;
a first well in the substrate;
a second well in the substrate;
a third well in the substrate between the first well and the second well, wherein the first, second and third wells are separated from each other, wherein a doping type of the first, second and third wells is the other one of the p-type or n-type doping;
a first terminal connected to the first well;
a second terminal connected to the second well;
an electrostatic discharge (ESD) clamp connected to the first and second terminals, wherein the ESD clamp is configured to clamp the first well and the second well at a clamp voltage during an ESD event; and
a transient voltage source connected to the third well, wherein the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.
2. The electronic device of claim 1 , further comprising:
complementary metal oxide semiconductor (CMOS) logic; and
a double diffused metal-oxide-semiconductor (DDMOS) transistor.
3. The electronic device of claim 1 , wherein the electronic device operates at least at 100 Volts.
4. The electronic device of claim 1 , wherein the ESD clamp comprises the transient voltage source.
5. The electronic device of claim 1 , wherein the first and the third wells are separated from each other by the substrate, and
wherein the second and third wells are separated from each other by the substrate.
6. The electronic device of claim 1 , further comprising:
a first plurality of layers having the same type doping as the substrate and located between the first and the third wells; and
a second plurality of layers having the same type doping as the substrate and located between the second and the third wells.
7. The electronic device of claim 6 , further comprising:
a first deep trench isolation (DTI) barrier located between the first and the third wells; and
a second DTI barrier located between the second and the third wells.
8. The electronic device of claim 7 , wherein the third well is in direct contact with the substrate.
9. The electronic device of claim 6 , wherein the first DTI barrier is in direct contact with the first well, and
wherein the second DTI barrier is in direct contact with the second well.
10. The electronic device of claim 9 , further comprising:
a third DTI barrier in direct contact with the first well; and
a fourth DTI barrier in direct contact with the second well.
11. The electronic device of claim 10 , wherein at least one of the first well and the second well is separated from the substrate by a buried layer.
12. The electronic device of claim 1 , wherein the ESD clamp comprises at least one of a Zener diode, a grounded-gate n-type MOSFET (metal-oxide-semiconductor field-effect transistors) or a silicon-controlled rectifier.
13. The electronic device of claim 12 , wherein the ESD clamp comprises a plurality of Zener diodes in series, and
wherein the Zener diodes form Zener-triggered Darlington clamps.
14. The electronic device of claim 13 , wherein the transient voltage source is generated from a voltage across at least one of the Zener diodes.
15. The electronic device of claim 13 , wherein the transient voltage source is generated from a voltage difference from a terminal of one of the Zener diodes and one of the first or second terminal.
16. The electronic device of claim 1 , wherein the first well, the second well and the substrate form a first transistor,
wherein the first well, the third well and the substrate form a second transistor, and
wherein the substrate is a base of the first transistor and is a base of the second transistor,
wherein the first transistor and the second transistor turn on during the ESD event.
17. The electronic device of claim 16 , wherein the substrate has p-type doping and the first, second and third wells have n-type doping.
18. The electronic device of claim 17 , wherein the first well is an emitter of the first transistor and an emitter of the second transistor.
19. The electronic device of claim 18 , wherein the second well is a collector of the first transistor and the third well is a collector of the second transistor.
20. The electronic device of claim 1 , wherein the first well, the substrate and the second well are configured to form a first transistor wherein a junction between the substrate and the second well form a collector of the first transistor,
wherein the first well, the substrate and the third well are configured to form a second transistor wherein a junction between the substrate and the third well form a collector of the second transistor,
wherein the first and second transistor are configured to turn on during the ESD event.