IP Library Granted Patent US 10,971,429
Granted Patent B2
US 10,971,429 · App. 16/798,874 · Granted Apr 6, 2021

Method for forming a semiconductor package

Inventors: Atapol Prajuckamol (Klaeng, TH); Soon Wei Wang (Seremban, MY); Hoe Kit Liew How Kiat Ley (Bukit Jalil, MY)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/4334H01L21/568H01L23/4951H01L23/4952H01L23/4985H01L23/49531H01L23/49575H01L24/01H01L24/03H01L24/05H01L21/561H01L23/3107H01L24/02H01L24/11H01L24/13H01L2224/02319H01L2224/02335H01L2224/02371H01L2224/02381H01L2224/0401H01L2224/04105H01L2224/05548H01L2224/05644H01L2224/05647H01L2224/05655H01L2224/1132H01L2224/11849H01L2224/12105H01L2224/16225H01L2224/73204H01L2224/73253H01L2224/85005H01L2224/96H01L2225/06517H01L2924/18165
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Quick Facts
Patent No.
US 10,971,429
App. No.
16/798,874
Granted
Apr 6, 2021
Kind
B2
Abstract

Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Claims (37)

1. A method of forming a semiconductor package comprising:

coupling a plurality of die to a non-electrically conductive layer;

coupling the non-electrically conductive layer to a metal sheet;

bonding a plurality of wires to a first side of each die;

bonding the plurality of wires to the metal sheet;

applying a mold compound over each die and the plurality of wires;

exposing an end of each wire of the plurality of wires and the non-electrically conductive layer through removing the metal sheet; and

singulating the mold compound to form a plurality of semiconductor packages;

wherein each semiconductor package of the plurality of semiconductor packages comprises a portion of the non-electrically conductive layer.

2. The method of claim 1 , wherein singulating the mold compound comprises sawing through the mold compound.

3. The method of claim 1 , further comprising coupling an electrical contact to each exposed end of each wire.

4. The method of claim 1 , wherein the semiconductor package does not comprise a lead frame.

5. The method of claim 3 , wherein an electrical contact comprises one of a bump, a stud, or a pad.

6. A method of forming a semiconductor package comprising:

coupling a plurality of die to a non-electrically conductive layer;

coupling the non-electrically conductive layer to a metal sheet;

bonding a plurality of wires to a first side of each die;

bonding the plurality of wires to the metal sheet;

applying a mold compound over each die and the plurality of wires;

exposing an end of each wire of the plurality of wires and the non-electrically conductive layer through separating the metal sheet; and

singulating the mold compound to form a plurality of semiconductor packages.

7. The method of claim 6 , wherein singulating the mold compound comprises sawing through the mold compound.

8. The method of claim 6 , further comprising coupling an electrical contact to each exposed end of each wire.

9. The method of claim 6 , wherein the semiconductor package does not comprise a lead frame.

10. The method of claim 8 , wherein an electrical contact comprises one of a bump, a stud, or a pad.

11. A method of forming a semiconductor package comprising:

coupling a plurality of die to a metal sheet, each die coupled to a layer between the die and the metal sheet;

bonding a plurality of wires to a first side of each die opposing the layer and bonding the plurality of wires to the metal sheet;

applying a mold compound over each die and the plurality of wires;

exposing an end of each wire of the plurality of wires through removing the metal sheet; and

singulating the mold compound to form a plurality of semiconductor packages;

wherein the layer comprised in each semiconductor package of the plurality of semiconductor packages is exposed through the mold compound.

12. The method of claim 11 , wherein removing the metal sheet comprises peeling away the metal sheet.

13. The method of claim 11 , further comprising forming a solder pad over each exposed end of each wire.

14. The method of claim 13 , wherein forming a solder pad over each exposed end of each wire comprises printing a solder pad.

15. The method of claim 11 , wherein the non-electrically conductive layer is a die flag.

16. The method of claim 11 , wherein the semiconductor package does not comprise a lead frame.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 052656, FRAME 0842 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064080/0149 →
SECURITY INTEREST Recorded May 13, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 052656/0842 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2020
From: PRAJUCKAMOL, ATAPOL; WANG, SOON WEI; LEY, HOE KIT LIEW HOW KAT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051903/0254 →
Continuity (3)
Continuation 16206057 · Nov 30, 2018
Division 15724413 · Oct 4, 2017
Related Publication 20200194340A1 · Jun 18, 2020