Semiconductor memory device
A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least eight threshold voltages, a first bit line connected to the first memory cell, a word line connected to a gate of the first memory cell, a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits, and an extra data latch circuit connected to the sense amplifier through a data bus. A verification operation for verifying the threshold voltage of the first memory cell is performed after a programming operation is performed on the first memory cell, and the verification operation includes seven verification operations during which the four data latch circuits, but not the extra data latch circuit, are accessed.
1. A semiconductor memory device comprising:
a first memory cell which is capable of being set to any one of at least eight threshold voltages;
a first bit line electrically connected to the first memory cell;
a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits;
an extra data latch circuit electrically connected to the sense amplifier through a bus; and
a controller configured to control a write operation that includes a programming operation for changing the threshold voltage of the first memory cell and a verification operation for verifying the threshold voltage of the first memory cell, wherein the controller is configured to cause, in the programming operation, the extra data latch circuit and at least one of the four data latch circuits to be accessed, and
wherein the controller is configured to cause, in the verification operation, the four data latch circuits, but not the extra latch circuit, to be accessed.
2. The device according to claim 1 , wherein the verification operation includes seven verification operations, the device further comprising:
a word line connected to a gate of the first memory cell, wherein
the seven verification operations include first, second, third, fourth, fifth, sixth, and seventh verification operations, and
during the first through seventh verification operations, respective first through seventh verification voltages, which are different from each other, are applied to the word line.
3. The device according to claim 2 , wherein the sense amplifier:
applies a charging voltage to the first bit line during two of the seven verification operations, and
does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.
4. The device according to claim 3 , further comprising:
a second memory cell that is capable of being set to any one of at least eight threshold voltages, and which has a gate connected to the word line; and
a second bit line connected to the second memory cell,
wherein the sense amplifier applies the charging voltage to the second bit line during two of the remaining five verification operations, and does not apply the charging voltage to the second bit line during the verification operations other than the two of the remaining five verification operations.
5. The device according to claim 4 , further comprising:
a third memory cell that is capable of being set to any one of the at least eight threshold voltages, and which has a gate connected to the word line; and
a third bit line connected to the third memory cell,
wherein the sense amplifier applies the charging voltage to the third bit line during a different two of the remaining five verification operations, and does not apply the charging voltage to the third bit line during the verification operations other than the different two of the remaining five verification operations.
6. The device according to claim 5 , further comprising:
a fourth memory cell that is capable of being set to any one of the at least eight threshold voltages, and which has a gate connected to the word line; and
a fourth bit line connected to the fourth memory cell,
wherein the sense amplifier applies the charging voltage to the fourth bit line during one of the seven verification operations other than said two of the seven verification operations, said two of the remaining five verification operations, and said different two of the remaining five verification operations, and does not apply the charging voltage to the fourth bit line during said two of the seven verification operations, said two of the remaining five verification operations, and said different two of the remaining five verification operations.
7. The device according to claim 2 , wherein the seven verification operations respectively correspond to seven of the at least eight threshold voltages.
8. The device according to claim 2 ,
wherein the first verification operation corresponds to the programming operation for writing first data in the first memory cell,
wherein the second verification operation corresponds to the programming operation for writing second data different from the first data in the first memory cell,
wherein the third verification operation corresponds to the programming operation for writing third data different from the first and second data in the first memory cell,
wherein the fourth verification operation corresponds to the programming operation for writing fourth data different from the first to third data in the first memory cell,
wherein the fifth verification operation corresponds to the programming operation for writing fifth data different from the first to fourth data in the first memory cell,
wherein the sixth verification operation corresponds to the programming operation for writing sixth data different from the first to fifth data in the first memory cell, and
wherein the seventh verification operation corresponds to the programming operation for writing seventh data different from the first to sixth data in the first memory cell.
9. The device according to claim 8 , wherein
the programming operation is carried out in a plurality of loops, and
the first through seventh verification operations are each carried out following a corresponding one of the programming operations.
10. The device according to claim 9 , wherein a programming voltage is increased in each subsequent loop.
11. A semiconductor memory device comprising:
a first memory cell which is capable of being set to any one of at least eight threshold voltages;
a first bit line electrically connected to the first memory cell;
a sense amplifier connected to the first bit line, wherein the sense amplifier has at least four data latch circuits;
an extra data latch circuit electrically connected to the sense amplifier through a bus; and
a controller configured to control a write operation that includes a programming operation for changing the threshold voltage of the first memory cell and a verification operation for verifying the threshold voltage of the first memory cell,
wherein the controller is configured to cause, in the programming operation, the extra data latch circuit and at least one of the four data latch circuits to be accessed,
wherein the controller is configured to cause, in the verification operation on the first memory cell, the four data latch circuits, but not the extra data latch circuit, to be accessed.
12. The device according to claim 11 , wherein the verification operation includes seven verification operations, the device further comprising:
a word line connected to a gate of the first memory cell,
wherein the seven verification operations include:
a first verification operation in which a first voltage is applied to the word line,
a second verification operation in which a second voltage higher than the first voltage is applied to the word line,
a third verification operation in which a third voltage higher than the second voltage is applied to the word line,
a fourth verification operation in which a fourth voltage higher than the third voltage is applied to the word line,
a fifth verification operation in which a fifth voltage higher than the fourth voltage is applied to the word line,
a sixth verification operation in which a sixth voltage higher than the fifth voltage is applied to the word line, and
a seventh verification operation in which a seventh voltage higher than the sixth voltage is applied to the word line, and
wherein the sense amplifier
applies a charging voltage to the first bit line during two of the seven verification operations, and
does not apply the charging voltage to the first bit line during the remaining five of the seven verification operations.
13. The device according to claim 12 , further comprising:
a second memory cell that is capable of being set to any one of the at least eight threshold voltages, and which has a gate connected to the word line; and
a second bit line connected to the second memory cell,
wherein the sense amplifier applies the charging voltage to the second bit line during two of the remaining five verification operations, and does not apply the charging voltage to the second bit line during the verification operations other than the two of the remaining five verification operations.
14. The device according to claim 13 , further comprising:
a third memory cell that is capable of being set to any one of the at least eight threshold voltages, and which has a gate connected to the word line; and
a third bit line connected to the third memory cell,
wherein the sense amplifier applies the charging voltage to the third bit line during a different two of the remaining five verification operations, and does not apply the charging voltage to the third bit line during the verification operations other than the different two of the remaining five verification operations.
15. The device according to claim 14 , further comprising:
a fourth memory cell that is capable of being set to any one of the at least eight threshold voltages, and which has a gate connected to the word line; and
a fourth bit line connected to the fourth memory cell,
wherein the sense amplifier applies the charging voltage to the fourth bit line during one of the seven verification operations other than said two of the seven verification operations, said two of the remaining five verification operations, and said different two of the remaining five verification operations, and does not apply the charging voltage to the fourth bit line during said two of the seven verification operations, said two of the remaining five verification operations, and said different two of the remaining five verification operations.
16. The device according to claim 11 , wherein the seven verification operations respectively correspond to seven of the at least eight threshold voltages.
17. The device according to claim 11 ,
wherein the first verification operation corresponds to the programming operation for writing first data in the first memory cell,
wherein the second verification operation corresponds to the programming operation for writing second data different from the first data in the first memory cell,
wherein the third verification operation corresponds to the programming operation for writing third data different from the first and second data in the first memory cell,
wherein the fourth verification operation corresponds to the programming operation for writing fourth data different from the first to third data in the first memory cell,
wherein the fifth verification operation corresponds to the programming operation for writing fifth data different from the first to fourth data in the first memory cell,
wherein the sixth verification operation corresponds to the programming operation for writing sixth data different from the first to fifth data in the first memory cell, and
wherein the seventh verification operation corresponds to the programming operation for writing seventh data different from the first to sixth data in the first memory cell.
18. The device according to claim 17 , wherein
the programming operation is carried out in a plurality of loops, and
the first to seventh verification operations are each carried out following a corresponding one of the programming operations.
19. The device according to claim 18 , wherein a programming voltage is increased in each subsequent loop.
20. The device according to claim 19 ,
wherein said at least four data latch circuits of the sense amplifier includes a first latch circuit and a second latch circuit,
wherein the extra data latch circuit is a third latch circuit that is connected to the sense amplifier via a switching element, and
wherein, during the programming operation,
the first latch circuit stores a first bit as first information,
the second latch circuit stores a second bit as second information,
the third latch circuit stores a third bit as third information, and
the sense amplifier applies the charging voltage to the first bit line based on the first information and second information, and not on the third information.