Split trench gate super junction power device

1. A power semiconductor device, comprising:

a semiconductor layer having a first conductivity type;

a pillar provided in the semiconductor layer and having a second conductivity type that is different than the first conductivity type;

a first trench gate provided in the pillar proximate to a first vertical edge of the pillar, the first trench gate bordering a first portion of the semiconductor layer to define a first channel aligned with the first vertical edge of the pillar;

a second trench gate provided in the pillar proximate to a second vertical edge of the pillar, the second vertical edge being on an opposing side of the pillar of the first vertical edge, and the second trench gate bordering a second portion of the semiconductor layer to define a second channel aligned with the second vertical edge of the pillar;

a first electrode provided over a first side of the semiconductor layer;

a second electrode provided over a second side of the semiconductor layer; and

a region of the second conductivity type provided in the pillar and between the first trench gate and the second trench gate, the region of the second conductivity type electrically coupling the pillar to the first electrode, the region of the second conductivity type being in contact with at least one of the first trench gate or the second trench gate,

wherein the first and second trench gates are separated by a shielding portion of the pillar, the shielding portion of the pillar and the region of the second conductivity type defining a current path for a reverse recovery current of the power semiconductor device.

2. The power semiconductor device of claim 1 , further comprising:

a third trench gate provided in the semiconductor layer and spaced apart from the pillar, the third trench gate having a first vertical surface and a second vertical surface.

3. The power semiconductor device of claim 2 , wherein the third trench gate defines a third channel and a fourth channel, respectively, and

wherein the third trench gate defines the third channel proximate to the first vertical surface of the third trench gate and the fourth channel proximate to the second vertical surface of the third trench gate.

4. The power semiconductor device of claim 3 , wherein the region of the second conductivity type is a first region, the power semiconductor device further comprising:

a well of the second conductivity type provided proximate to the first electrode; and

a plurality of regions of the second conductivity type provided in the well, the plurality of regions including the first region, a second region, a third region, and a fourth region that make first, second, and third, and fourth Ohmic contacts with the first electrode, respectively.

5. The power semiconductor device of claim 4 , wherein the second region is proximate to the first vertical edge of the pillar, the third region is provided between the second and third trench gates, and the fourth region is provided proximate the second vertical surface of the third trench gate.

6. The power semiconductor device of claim 5 , wherein the second, third, and fourth regions define current paths for a forward current of the power semiconductor device.

7. The power semiconductor device of claim 1 , wherein the region of the second conductivity type is a first region, the power semiconductor device further comprising:

a plurality of wells of the second conductivity type provided proximate to the first electrode;

a plurality of regions of the first conductivity type; and

a plurality of regions of the second conductivity type provided in the plurality of wells, the plurality of regions of the second conductivity type including the first region, a second region, and a third region that make first, second, and third Ohmic contacts with the first electrode, respectively.

8. The power semiconductor device of claim 7 , wherein the second region is proximate to the first vertical edge of the pillar and the third region is proximate to the second vertical edge of the pillar.

9. The power semiconductor device of claim 8 , wherein the second and third regions define current paths for a forward current.

10. The power semiconductor device of claim 1 , wherein the first trench gate includes a gate electrode and a gate dielectric material, the first gate dielectric material including a gate dielectric layer and a gate dielectric spacer, the gate dielectric layer provided over the first channel and having a thickness of no more than 0.15 um, the gate dielectric spacer having a thickness of at least 0.2 um.

11. The power semiconductor device of claim 10 , wherein the gate dielectric material is an oxide and encapsulates the gate electrode.

12. The power semiconductor device of claim 1 , wherein the first trench gate includes a gate electrode and a gate oxide material encapsulating the gate electrode,

wherein the first trench gate includes first, second, third, and fourth sides, the first side corresponding to the first vertical edge of the pillar and defining the first channel of the first trench gate, the second side corresponding to an upper surface of the first trench gate, the third side corresponding to an opposing side of the first side, and the fourth side corresponding to a bottom surface of the first trench gate,

wherein the gate oxide material has first, second, third, and fourth thicknesses at the first, second, third, and fourth sides of the first trench gate, respectively, and

wherein the first thickness is no more than 0.15 um and the second, third, and fourth thicknesses are at least 0.20 um.

13. The power semiconductor device of claim 1 , wherein the power semiconductor device is a MOSFET and the pillar provides a charge balance area,

wherein the first conductivity type is an N conductivity type, and the second conductivity type is a P conductivity type, and

wherein the power semiconductor device is configured to handle a breakdown voltage of at least 600V and has an on-resistance of no more than 10 mOhm/cm 2 .

14. The power semiconductor device of claim 1 , wherein the pillar is a first pillar, and the power semiconductor device further comprising:

a second pillar provided in the semiconductor layer and being adjacent to the first pillar; and

a third trench gate provided between the first pillar and the second pillar and being spaced apart from the first pillar and the second pillar, the third trench gate including a gate electrode and a gate dielectric material.

15. A power semiconductor device including a plurality of unit cells, each unit cell comprising:

a first trench gate provided in a first pillar, the first trench gate having a first side aligned with a vertical edge of the first pillar and a second side facing an interior of the first pillar;

a second trench gate provided in a second pillar, the second trench gate having a first side aligned with a vertical edge of the second pillar and a second side facing an interior of the second pillar, the first and second pillars being adjacent pillars;

a third trench gate provided between the first and second trench gates, the third trench gate extending into a drift region; and

first, second, third, and fourth heavily doped regions making Ohmic contacts with an electrode, the first heavily doped region being provided in the first pillar, the second heavily doped region provided between the first and third trench gates, the third heavily doped region provided between the second and third trench gates, and the fourth heavily doped region provided within the second pillar.

16. The power semiconductor device of claim 15 , wherein the second and third heavily doped regions provide current paths for a forward current, and the first and fourth heavily doped regions provide current paths for a reverse recovery current.

17. A method for forming a power semiconductor device, the method comprising:

providing an epi layer over a substrate;

forming a well and a pillar in the epi layer;

etching the pillar and the epi layer to form first, second, and third trenches, the first and second trenches being provided in the pillar, the third trench being provided in the epi layer spaced apart from the pillar;

forming first, second and third trench gates in the first, second, and third trenches, respectively, the first trench gate having a first side aligned with a first vertical edge of the pillar, the second trench gate having a first side aligned with a second vertical edge of the pillar opposite the first vertical edge of the pillar;

forming first, second, third, and fourth heavily doped regions in the well and the pillar, the second heavily doped region being provided within the pillar and between the first and second trench gates;

providing a first metal electrode over a first side of the epi layer and making Ohmic contacts with the first, second, third, and fourth heavily doped regions; and

providing a second metal electrode over a second side of the epi layer.

18. The method of claim 17 , wherein the first, third, and fourth heavily doped regions provide current paths for a forward current of the power semiconductor device, and the second heavily doped region provides a current path for a reverse recovery current of the power semiconductor device.

19. The method of claim 17 , wherein the first trench gate further includes second, third, and fourth sides, the first trench gate having a gate electrode and a gate oxide material encapsulating the gate electrode,

wherein the gate oxide material has first, second, third, and fourth thicknesses at the first, second, third, and fourth sides of the first gate trench, respectively,

wherein the first side defines a channel for the first trench gate, the second side corresponds to an upper surface of the first trench gate, the third side corresponds to an opposing side of the first side, and the fourth side corresponds to a bottom surface of the first trench gate,

wherein the first thickness is no more than 0.15 um, and

wherein the second, third, and fourth thicknesses are at least 0.20 um.