Process of forming an electronic device including a transistor structure
An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.
1. A process of forming an electronic device including a high electron mobility transistor, the process comprising:
providing a workpiece including a substrate, a first layer overlying the substrate, and a channel layer including a compound semiconductor material and overlying the first layer, wherein a heterojunction is at an interface between the first layer and the channel layer; and
implanting H + ions or He + ions into an implant region that includes at least a portion of a region of the workpiece between a source region of the high electron mobility transistor and a gate region of the high electron mobility transistor, wherein the implanting the H + ions or the He + ions forms crystal defects that form a leakage path across the heterojunction.
2. The process of claim 1 , wherein the implanting the H + ions or the He + ions is performed such that the implant region includes a gate region of the high electron mobility transistor.
3. The process of claim 2 , further comprising forming a gate electrode of the high electron mobility transistor over the gate region.
4. The process of claim 3 , wherein the implanting the H + ions or the He + ions is performed before the forming the gate electrode.
5. The process of claim 2 , wherein the implanting the H + ions or the He + ions is performed such that the implant region includes the source region and a drain region of the high electron mobility transistor.
6. The process of claim 1 , further comprising forming a source electrode of the high electron mobility transistor over the source region, and forming a drain electrode of the high electron mobility transistor over the drain region.
7. The process of claim 6 , wherein after the forming the source electrode and the forming the drain electrode, within each of the source region and the drain region, the channel layer has a carrier impurity concentration less than 1×10 16 atoms/cm 3 .
8. The process of claim 6 , wherein:
the providing the workpiece further comprises a barrier layer overlying the channel layer; and
after the forming the source electrode and the forming the drain electrode, within each of the source region and the drain region, the barrier layer has a carrier impurity concentration of at most 5×10 16 atoms/cm 3 .
9. The process of claim 6 , wherein the implanting the H + ions or the He + ions is performed after the forming the source electrode and the forming the drain electrode.
10. The process of claim 9 , wherein the forming the source electrode and the forming the drain electrode comprises:
forming a conductive layer over the workpiece, wherein the conductive layer includes at least 50 wt % aluminum; and
patterning the conductive layer to form the source electrode and the drain electrode.
11. The process of claim 6 , further comprising:
forming a source terminal over and electrically connected to the source electrode, wherein the source terminal includes a portion that covers a first part of the region of the workpiece between the source region and the drain region, and the implanting the H + ions or the He + ions is performed after the forming the source terminal, or
forming a drain terminal over and electrically connected to the drain electrode, wherein the drain terminal includes a portion that covers a second part of the region of the workpiece between the source region and the drain region, and the implanting the H + ions or the He + ions is performed after the forming the drain terminal.
12. The process of claim 1 , wherein the implanting the H + ions or the He + ions is performed such that the implant region includes the source region, a drain region of the high electron mobility transistor, and all of a region between the source region and the drain region.
13. The process of claim 1 , wherein the implanting the H + ions or He + ions is performed to an implant dose in a range of 1×10 14 ions/cm 2 to 5×10 14 ions/cm 2 .
14. The process of claim 1 , wherein a highest temperature to which the workpiece is exposed after the implanting the H + ions or the He + ions is at most 600° C.
15. A process of forming an electronic device including a high electron mobility transistor, the process comprising:
providing a workpiece including a substrate, a first layer overlying the substrate, and a channel layer including a compound semiconductor material and overlying the first layer, wherein a heterojunction is at an interface between the channel layer and the first layer;
forming a source electrode over a portion of the channel layer within a source region of the high electron mobility transistor;
forming a drain electrode over a portion of the channel layer within a drain region of the high electron mobility transistor; and
implanting H + ions or He + ions into an implant region to form crystal defects within the high electron mobility transistor, wherein the crystal defects form a leakage path across the heterojunction, wherein the implant region includes at least the source region of the high electron mobility transistor,
wherein after the forming the source electrode and the forming the drain electrode, within each of the source region and the drain region, the channel layer has a carrier impurity concentration less than 1×10 16 atoms/cm 3 .
16. The process of claim 15 , wherein:
the providing the workpiece further comprises a barrier layer overlying the channel layer, and
after the forming the source electrode and the forming the drain electrode, within each of the source region and the drain region, the barrier layer has a carrier impurity concentration less than 1×10 16 atoms/cm 3 .
17. The process of claim 15 , wherein the implanting the H + ions or the He + ions is performed such that the implant region includes at least a gate region of the workpiece.
18. The process of claim 15 , wherein the implanting the H + ions or the He + ions is performed such that the implant region includes the source region, the drain region, and all of a region between the source region and the drain region.