Three-dimensional memory devices and methods for forming the same
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.
1. A memory device, comprising:
a stack structure comprising interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction; and
a channel structure extending in the stack structure along the vertical direction and divided into a lower portion and an upper portion along the vertical direction, a width of the channel structure in the lower portion being less than a width of the channel structure in the upper portion,
wherein:
thicknesses of conductor layers in the lower portion are less than thicknesses of conductor layers in the upper portion,
thicknesses of dielectric layers in the lower portion are greater than thicknesses of dielectric layers in the upper portion,
a thickness of at least one of the plurality of conductor layers is nominally proportional to a width of the channel structure at a same depth, and
a thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at a same depth.
2. The memory device of claim 1 , wherein:
the thickness of each of the conductor layers in the lower portion is the same; and
the thickness of each of the conductor layers in the upper portion is the same.
3. The memory device of claim 1 , wherein:
the thickness of each of the dielectric layers in the lower portion is the same; and
the thickness of each of the dielectric layers in the upper portion is the same.
4. The memory device of claim 1 , wherein:
the thicknesses of the conductor layers in the lower portion increase as the depth decreases; and
the thicknesses of the dielectric layers in the lower portion decrease as the depth decreases.
5. The memory device of claim 1 , wherein:
in the lower portion, the conductor layers and the dielectric layers comprise at least one first division along the vertical direction, each first division comprising at least one conductor layer and at least one dielectric layer.
6. The memory device of claim 5 , wherein:
in each of the at least one first division, the thickness of each conductor layer is the same, and the thickness of each dielectric layer is the same;
the thicknesses of the conductor layers in the at least one first division increase as the depth decreases; and
the thicknesses of the dielectric layers in the at least one first division decrease as the depth decreases.
7. The memory device of claim 1 , wherein:
the thicknesses of the conductor layers in the upper portion decrease as the depth increases; and
the thicknesses of the dielectric layers in the upper portion increase as the depth increases.
8. The memory device of claim 1 , wherein:
in the upper portion, the conductor layers and the dielectric layers comprise at least one second division along the vertical direction, each second division comprising at least one conductor layer and at least one dielectric layer.
9. The memory device of claim 8 , wherein:
in each of the at least one second division, the thickness of each conductor layer is the same, and the thickness of each dielectric layer is the same;
the thicknesses of the conductor layers in the at least one second division decrease as the depth increases; and
the thicknesses of the dielectric layers in the at least one second division increase as the depth increases.
10. A memory device, comprising:
a stack structure comprising interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction; and
a channel structure extending in the stack structure and divided into a plurality of portions along the vertical direction,
wherein:
the plurality of portions comprise a lower portion and an upper portion, a width of the channel structure in the lower portion being less than a width of the channel structure in the upper portion,
thicknesses of conductor layers in the lower portion are less than thicknesses of conductor layers in the upper portion,
thicknesses of dielectric layers in the lower portion are greater than thicknesses of dielectric layers in the upper portion,
thicknesses of conductor layers corresponding to each of the plurality of portions are nominally proportional to a width of the portion, and
thicknesses of dielectric layers corresponding to each of the plurality of portions are nominally inversely proportional to a width of the channel structure in the respective portion.
11. The memory device of claim 10 , wherein:
the thickness of each of the conductor layers in the lower portion is the same; and
the thickness of each of the conductor layers in the upper portion is the same.
12. The memory device of claim 10 , wherein:
the plurality of portions further comprise a narrower portion between a top surface and a bottom surface of the stack structure, a width of the narrower portion being less than a width of a remaining portion of the channel structure;
the thicknesses of the conductor layers corresponding to the narrower portion are less than thicknesses of conductor layers corresponding to the remaining portion of the channel structure; and
the thicknesses of the dielectric layers corresponding to the narrower portion are greater than thicknesses of conductor layers corresponding to the remaining portion of the channel structure.
13. The memory device of claim 10 , wherein:
the thickness of each of the dielectric layers in the lower portion is the same, and
the thickness of each of the dielectric layers in the upper portion is the same.
14. The memory device of claim 10 , wherein:
the thicknesses of the conductor layers in the lower portion increase as a depth decreases, and
the thicknesses of the dielectric layers in the lower portion decrease as the depth decreases.
15. The memory device of claim 10 , wherein:
in the lower portion, the conductor layers and the dielectric layers comprise at least one first division along the vertical direction, each first division comprising at least one conductor layer and at least one dielectric layer, and
in each of the at least one first division, the thickness of each conductor layer is the same, and the thickness of each dielectric layer is the same.
16. The memory device of claim 10 , wherein:
in the upper portion, the conductor layers and the dielectric layers comprise at least one second division along the vertical direction, each second division comprising at least one conductor layer and at least one dielectric layer, and
in each of the at least one second division, the thickness of each conductor layer is the same, and the thickness of each dielectric layer is the same.
17. A memory device, comprising:
a stack structure comprising interleaved a plurality of conductor layers and a plurality of dielectric layers along a vertical direction; and
a channel structure extending in the stack structure along the vertical direction,
wherein:
the channel structure comprises a deformed portion between a top surface and a bottom surface of the stack structure, a width of the deformed portion being different from a width of a remaining portion of the channel structure,
thicknesses of the conductor layers corresponding to the remaining portion are equal, and thicknesses of the conductor layers corresponding to the deformed portion are different from the thicknesses of the conductor layers corresponding to the remaining portion, and
thicknesses of the dielectric layers corresponding to the remaining portion are equal, and thicknesses of the dielectric layers corresponding to the deformed portion are different from the thicknesses of the dielectric layers corresponding to the remaining portion.
18. The memory device of claim 17 , wherein:
the deformed portion is a narrower portion, a width of the narrower portion being less than a width of the remaining portion of the channel structure,
the thicknesses of the conductor layers corresponding to the narrower portion are less than the thicknesses of the conductor layers corresponding to the remaining portion, and
the thicknesses of the dielectric layers corresponding to the narrower portion are greater than the thicknesses of the dielectric layers corresponding to the remaining portion.
19. The memory device of claim 17 , wherein:
the deformed portion is a wider portion, a width of the wider portion being greater than a width of the remaining portion of the channel structure,
the thicknesses of the conductor layers corresponding to the wider portion are greater than the thicknesses of the conductor layers corresponding to the remaining portion, and
the thicknesses of the dielectric layers corresponding to the wider portion are less than the thicknesses of the dielectric layers corresponding to the remaining portion.
20. The memory device of claim 17 , wherein:
the channel structure further comprises an upper portion above the deformed portion and a lower portion below the deformed portion.