MULTI-PROCESSOR SYSTEM AND METHOD UTILIZING DISCRETE COMPONENT PROCESSOR ELEMENTS
A system and method for the dynamic, run-time configuration of logic core register files, and the provision of an associated execution context. The dynamic register tiles as well as the associated execution context information are software-defined so as to be virtually configured in random-access memory. This virtualization of both the processor execution context and register files enables the size, structure and performance to be specified at run-time and tailored to the specific processing, instructions and data associated with a given processor state or thread, thereby minimizing both the aggregate memory required and the context switching time. In addition, the disclosed system and method provides for processor virtualization which further enhances the flexibility and efficiency.
1 . A multi-core processing system comprising:
a plurality of discrete processing arrangements, each comprising a core memory and an associated core logic, the core memory adapted to store at least one set of executable instructions, and an associated a core logic, comprised of at least one processor and adapted to execute the instructions; and
at least one physical execution context stored in a specific portion of an addressable memory and comprised of information indicative of a particular processor state and at least one pointer to at least one of the plurality of discrete processing arrangements, wherein the capacity of the specific portion of the addressable memory storing the physical execution context is based upon the memory space required to store, the information indicative of a particular processor state and the at least one pointer, wherein the physical execution context is adapted to:
link to at least one particular processing arrangement based upon the at least one pointer; and
provide the information indicative of a particular processor state to the particular processing arrangement so as to enable the core logic of the particular processing arrangement to execute at least one set of executable instructions.
2 . The system of claim 1 wherein the core memory is adapted to store a plurality of instruction sets, each of which defines a separate functionality for the associated core logic.
3 . The system of claim 2 wherein the core logic is particularly adapted to process instruction sets associated with the functionality of at least one of the stored plurality of instruction sets.
4 . The system of claim 1 wherein the at least one pointer is adapted to sequentially point to multiple discrete processing arrangements based upon the physical execution context.
5 . The system of claim 1 wherein the addressable memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.
6 . The system of claim 1 wherein the specific portion of the addressable memory has a capacity equal to the minimum memory space required to store the physical execution context.
7 . The system of claim 1 wherein the at least one set of executable instructions comprises instructions for processor initialization.
8 . A method of multi-core processing comprising the steps of:
storing at least one set of executable instructions in each of a plurality of core memories, wherein each core memory is associated with a core logic comprised of at least one processor and adapted to execute the stored instructions;
storing at least one physical execution context in a. specific portion of an addressable memory, the physical execution context comprising information indicative of a particular processor state and at least one pointer to at least one of the plurality of discrete processing arrangements, wherein the capacity of the specific portion of the addressable memory storing the physical execution context is based upon the memory space required to store the information indicative of a particular processor state and the at least one pointer; and
providing, based upon the at least one pointer, the information indicative of a particular processor state to a particular one of the core memories and associated core logic so as to enable the core logic of the particular processing arrangement to execute at least one set of executable instructions.
9 . The method of claim 8 wherein the at least one pointer is adapted to sequentially point to multiple discrete processing arrangements based upon the physical execution context.
10 . The method of claim 8 wherein the addressable memory comprises at least one of the following:
static random-access memory;
dynamic random-access memory; and
non-volatile memory.
11 . The method of claim 8 wherein the specific portion of the addressable memory has a capacity equal to the minimum memory space required to store the physical execution context.
12 . The method of claim 8 wherein the at least one set of executable instructions comprises instructions for processor initialization.
13 . The method of claim 8 wherein the core memory is adapted to store a plurality of instruction sets, each of which defines a separate functionality for the associated core logic.
14 . The method of claim 13 wherein the core logic is particularly adapted to process instruction sets associated with the functionality of at least one of the stored plurality of instruction sets.