Systems and methods for magnetic field sensors with self-test
Systems, methods, and apparatuses for magnetic field sensors with self-test include a detection circuit to detect speed and direction of a target. One or more circuits to test accuracy of the detected speed and direction may be included. One or more circuits to test accuracy of an oscillator may also be included. One or more circuits to test the accuracy of an analog-to-digital converter may also be included. Additionally, one or more IDDQ and/or built-in-self test (BIST) circuits may be included.
1. An apparatus comprising:
a detection circuit to detect speed and direction of a target, the detection circuit comprising:
one or more output terminals to provide output signals representing the detected speed and/or the detected direction; and
an oscillator; and
a first test circuit configured to determine whether the oscillator is operating within a predetermined frequency range; and
a second test circuit configured to measure a voltage level of a voltage ramp signal from the first test circuit after the voltage ramp signal has decayed for a period of time, wherein the second test circuit comprises:
a first comparator to compare the voltage ramp signal to a predetermined upper voltage; and
a second comparator to compare the voltage ramp signal to a predetermined lower voltage.
2. The apparatus of claim 1 , wherein the a first test circuit is coupled to the oscillator to determine whether the oscillator is operating within a predetermined frequency range, and
wherein the first test circuit is configured to assert an error condition on at least one of the output terminals if the oscillator is not operating within the predetermined frequency range.
3. The apparatus of claim 1 , wherein the first test circuit comprises a ramp generator that generates the voltage ramp signal that decays over time and resets upon detection of an edge of an output signal of the oscillator.
4. The apparatus of claim 3 , further comprising a voltage level test circuit to measure a voltage level of the voltage ramp signal after the voltage ramp signal has decayed for a period of time.
5. The apparatus of claim 4 , wherein the period of time comprises a period of the oscillator.
6. The apparatus of claim 1 , wherein the first test circuit comprises a switched capacitor resistor having at least one switch controlled by an output of the oscillator.
7. The apparatus of claim 1 , further comprising at least one magnetoresistance element configured to provide a signal indicative of changes in a magnetic field resulting from movement of the target.
8. The apparatus of claim 1 , further comprising an analog-to-digital converter (ADC) comprising an input port and an output port, wherein the input port is configured to receive a signal from at least one magnetoresistance element.
9. The apparatus of claim 8 , further comprising an ADC test circuit connected to the input port and the output port of the ADC, wherein the ADC test circuit is configured to:
inject a test signal into the input port of the ADC;
measure, at the output port of the ADC, an ADC output signal; and
determine whether the ADC output signal is an expected value; and
generate an error signal in response to the ADC output signal not being the expected value.
10. The apparatus of claim 9 , further comprising a processor configured to:
receive the ADC output signal;
receive the error signal; and
send an error condition to the one or more output terminals by altering voltages on the output signals in response to receiving the error signal, wherein the processor is connected to the output port of the ADC and the ADC test circuit.
11. The apparatus of claim 10 , wherein the first test circuit is further configured to calculate an average value of an output of the ADC circuit and compare the calculated average value to a predetermined value.
12. An apparatus comprising:
a detection circuit to detect speed and direction of a target, the detection circuit comprising:
one or more output terminals to provide output signals representing the detected speed and/or the detected direction; and
an oscillator;
a first test circuit, coupled to the oscillator, configured to determine whether the oscillator is operating within a predetermined frequency range and configured to assert an error condition on at least one of the output terminals if the oscillator is not operating within the predetermined frequency range, wherein the first test circuit comprises a ramp generator that generates a voltage ramp signal that decays over time and resets upon detection of an edge of an output signal of the oscillator; and
a second test circuit configured to measure a voltage level of the voltage ramp signal after the voltage ramp signal has decayed for a period of time, wherein the second test circuit comprises:
a first comparator to compare the voltage ramp signal to a predetermined upper voltage; and
a second comparator to compare the voltage ramp signal to a predetermined lower voltage.
13. The apparatus of claim 12 , wherein the first test circuit comprises a switched capacitor resistor having at least one switch controlled by an output of the oscillator output.
14. The apparatus of claim 12 , wherein the period of time comprises a period of the oscillator.
15. The apparatus of claim 12 , further comprising at least one magnetoresistance element configured to provide a signal indicative of changes in a magnetic field resulting from movement of the target.
16. The apparatus of claim 12 , further comprising an analog-to-digital converter (ADC) comprising an input port and an output port, wherein the input port is configured to receive a signal from at least one magnetoresistance element.
17. The apparatus of claim 16 , further comprising an ADC test circuit connected to the input port and the output port of the ADC, wherein the ADC test circuit is configured to:
inject a test signal into the input port of the ADC;
measure, at the output port of the ADC, an ADC output signal; and
determine whether the ADC output signal is an expected value; and
generate an error signal in response to the ADC output signal not being the expected value.
18. The apparatus of claim 17 , further comprising a processor configured to:
receive the ADC output signal;
receive the error signal; and
send an error condition to the one or more output terminals by altering voltages on the output signals in response to receiving the error signal, wherein the processor is connected to the output port of the ADC and the ADC test circuit.
19. The apparatus of claim 18 , wherein the first test circuit is further configured to calculate an average value of an output of the ADC circuit and compare the calculated average value to a predetermined value.