Systems and method for improving operating characteristics of displays

1. A display system, comprising:

a display; and

a display driver, wherein the display driver is configured to send a bit-plane to the display according to a display table;

wherein each row of the display table includes a sequence of bit-planes associated with one of a plurality of phase values;

wherein each sequence of bit-planes includes a number of 1-values and a number of 0-values associated with a respective one of the plurality of phase values;

wherein, for each sequence of bit-planes where the number of 1-values is greater than one:

the number of 1-values are distributed in the sequence of bit-planes such that one or more groups of one or more 1-values are spaced apart from one another by one or more groups of one or more 0-values; and

wherein each of the one or more groups of one or more 1-values has approximately a same number of bit-planes and each of the one or more groups of one or more 0-values has approximately a same number of bit-planes.

2. The display system of claim 1 , wherein a time of each bit-plane is such that the sequence of bit-planes repeats an integer number of times within a frame time.

3. The display system of claim 1 , wherein a voltage offset is applied to at least one bit-plane in a sequence of bit-planes.

4. The method of claim 3 , further comprising:

adjusting a time of each bit-plane such that the sequence of bit-planes repeats an integer number of times within a frame time.

5. The method of claim 3 , further comprising:

measuring a phase ripple using at least one of the sequences of bit-planes;

applying a voltage offset to at least one of the bit-planes in at least one of the sequences of bit-planes;

measuring a phase ripple using the modified at least one of the sequences of bit-planes; and

selecting from the at least one of the sequences of bit-planes and the modified at least one of the sequences of bit-planes based on which measured a lower phase ripple.

6. A display system, comprising:

a display; and

a display driver, wherein the display driver is configured to send a bit-plane to the display according to a display table;

wherein each row of the display table includes a sequence of bit-planes associated with one of a plurality of phase shift values;

wherein each sequence of bit-planes includes a number of 1-values and a number of 0-values associated with a respective one of the plurality of phase shift values;

wherein, for each sequence of bit-planes where a number P of 1-values is greater than one and less than 2 n −2, the number of 1-values are distributed across a length of the sequence of bit-planes according to a spacing D that is determined as 2 n /P, where the length of the sequence of bit-planes is 2 n and P represents the number of 1-values in a sequence of bit-planes.

7. The display system of claim 6 , wherein, for each sequence of bit-planes where the number of 1-values is greater than one and less than 2 n −2, the number of 1-values are distributed across the length of the sequence of bit-planes such that one or more groups of one or more 1-values are spaced apart from one another by one or more groups of one or more 0-values.

8. The display system of claim 6 , wherein, for each sequence of bit-planes where the number of 1-values is greater than one and less than 2 n −2, each of the one or more groups of one or more 1-values is the same or within one bit-plane of each of the one or more groups of one or more 1-values.

9. The display system of claim 7 , wherein, for each sequence of bit-planes where the number of 1-values is greater than one and less than 2 n −2, each of the one or more groups of one or more 0-values is the same or within one bit-plane of each of the one or more groups of one or more 0-values.

10. The display system of claim 6 , wherein the plurality of phase shift values is 2 n phase shift values.

11. The display system of claim 6 , wherein each of the plurality of phase shift values is associated with the number P in a range 0, 1, . . . , 2 n −1, wherein P represents the number of 1-values in a sequence of bit-planes associated with one of the plurality of phase shift values and 2 n −P represents the number of 0-values in the sequence of bit-planes associated with the one of the plurality of phase shift values.

12. The display system of claim 6 , wherein:

if the spacing D is an integer, consecutive 1-values in a sequence of bit-planes are spaced apart from one another by D bit-planes; and

if the spacing D is not an integer, consecutive 1-values in a sequence of bit-planes are spaced apart from one another by int(D) bit-planes or int(D)+1 bit-planes.

13. The display system of claim 12 , wherein an integer number of sequences of bit-planes in a frame are rotated by an integer value to decrease at least one of a number of on-to-off transitions and a number of off-to-on transitions in the frame.

14. A method for forming a display table including a plurality of bit-plane sequences each associated with one of a plurality of phase shift values, comprising:

determining a bit plane resolution 2 n ;

determining 2 n phase shift values, wherein each of the phase shift values is associated with a number P in a range 0, 1, . . . , 2 n −1, wherein P represents a number of 1-values in a sequence of bit-planes associated with one of the phase shift values and 2 n −P represents a number of 0-values in the sequence of bit-planes associated with the one of the phase shift values; and

for each of the phase shift values associated with a number P in a range of 2, . . . , 2 n −2;

determining a spacing D as 2 n /P; and

determining a sequence of bit-planes such that the number of 1-values are distributed across a length of the sequence of bit-planes according to the spacing D.

15. The method of claim 14 , wherein:

if the spacing D is an integer, spacing consecutive 1-values in a sequence of bit-planes apart from one another by D bit-planes; and

if the spacing D is not an integer, spacing consecutive 1-values in a sequence of bit-planes apart from one another by int(D) bit-planes or int(D)+1 bit-planes.

16. The method of claim 14 , wherein if the spacing Di s not an integer, determining a sequence of bit-planes includes determining a plurality of sequences of bit-planes.

17. The method of claim 15 , further comprising:

calculating an average difference between adjacent 1-values in each of the plurality of sequences of bit-planes, wherein the average difference between adjacent 1-values includes a difference between a last 1-value in a sequence of biplanes and a first 1-value in a subsequent repeated sequence of bit-planes; and

selecting one of the plurality of sequences of bit-planes having a lowest average difference.

18. The method of claim 15 , further comprising selecting one of the plurality of sequences of bit-planes having a second 1-value earlier in the sequence.

19. The method of claim 18 , further comprising rotating an integer number of sequences of bit-planes in a frame by an integer value to decrease at least one of a number of on-to-off transitions and a number of off-to-on transitions in the frame.

20. The method of claim 19 , wherein applying a voltage offset to at least one of the bit-planes in the at least one of the sequences of bit-planes comprises the applying a positive voltage offset or a negative voltage offset.