Engineered substrate architecture for InGaN red micro-LEDs

1. A light emitting diode (LED) device comprising:

a substrate; and

a plurality of mesa structures on the substrate, each mesa structure of the plurality of mesa structures comprising:

a layer of a first semiconductor material grown on the substrate;

a porous layer of the first semiconductor material on the layer of the first semiconductor material, the porous layer characterized by an areal porosity equal to or greater than 15%;

a layer of a second semiconductor material on the porous layer, the second semiconductor material characterized by a lattice constant greater than a lattice constant of the first semiconductor material;

an active region on the layer of the second semiconductor material, the active region configured to emit red light, wherein the active region includes at least one quantum well layer including InGaN;

a p-contact layer on the active region;

a dielectric layer on sidewalls of the p-contact layer and the active region; and

an n-contact layer in physical contact with at least a portion of sidewalls of the layer of the second semiconductor material, wherein the n-contact layer is on sidewalls of the porous layer and at least a portion of sidewalls of the layer of the first semiconductor material.

2. The LED device of claim 1 , wherein:

the first semiconductor material includes a first III-nitride semiconductor material; and

the second semiconductor material includes a second III-nitride semiconductor material.

3. The LED device of claim 2 , wherein the first semiconductor material includes GaN and the second semiconductor material includes InGaN.

4. The LED device of claim 1 , wherein the at least one quantum well layer includes In x Ga 1-x N, where x>0.2.

5. The LED device of claim 1 , wherein the layer of the second semiconductor material includes In x Ga 1-x N, where 0<x≤0.2.

6. The LED device of claim 1 , wherein the dielectric layer is between the n-contact layer and the sidewalls of the p-contact layer and the active region.

7. The LED device of claim 1 , wherein the dielectric layer is on a portion of the sidewalls of the layer of the second semiconductor material.

8. The LED device of claim 1 , wherein the areal porosity of the porous layer is between 30% and 90%.

9. The LED device of claim 1 , wherein the layer of the second semiconductor material has a lower resistance than the porous layer.

10. The LED device of claim 1 , wherein a thickness of the porous layer is greater than 50 nm.

11. The LED device of claim 1 , wherein the substrate includes a buffer layer and a sapphire or silicon substrate layer.

12. The LED device of claim 1 , wherein:

the layer of the first semiconductor material and the porous layer are n-doped; and

a difference between a doping density of the porous layer and the doping density of the layer of the first semiconductor material is less than 5%.

13. The LED device of claim 1 , further comprising a patterned dielectric layer on the substrate, wherein:

the substrate includes a buffer layer;

the patterned dielectric layer is on the buffer layer and includes a plurality of apertures to expose portions of the substrate; and

the layer of the first semiconductor material in each mesa structure of the plurality of mesa structures is grown on a respective portion of the buffer layer through a respective aperture of the plurality of apertures.

14. The LED device of claim 1 , further comprising a driver backplane bonded to the plurality of mesa structures, the driver backplane including driver circuits electrically connected to the p-contact layer and the n-contact layer of each mesa structure of the plurality of mesa structures.

15. A method of fabricating a light emitting diode (LED) device, the method comprising:

forming a plurality of precursor mesa structures on a substrate, each precursor mesa structure of the plurality of precursor mesa structures comprising:

a layer of a first semiconductor material grown on the substrate;

a porous layer of the first semiconductor material on the layer of the first semiconductor material, the porous layer characterized by an areal porosity equal to or greater than 15%; and

a layer of a second semiconductor material on the porous layer, the second semiconductor material characterized by a lattice constant greater than a lattice constant of the first semiconductor material;

forming an LED layer stack on each precursor mesa structure of the plurality of precursor mesa structures, the LED layer stack comprising:

an active region on the layer of the second semiconductor material, the active region configured to emit red light; and

a p-contact layer on the active region;

etching, using a mask layer, the LED layer stack to remove peripheral regions of the LED layer stack and to form one or more pixel mesa structures on each precursor mesa structure of the plurality of precursor mesa structures;

forming a dielectric layer on sidewalls of each pixel mesa structures of the one or more pixel mesa structures;

etching, using the mask layer on the one or more pixel mesa structure, the plurality of precursor mesa structures on the substrate; and

forming an n-contact layer on sidewalls of each pixel mesa structure of the one or more pixel mesa structures, the n-contact layer in physical contact with the dielectric layer, at least a portion of sidewalls of the layer of the second semiconductor material, and sidewalls of the porous layer.

16. The method of claim 15 , wherein forming the plurality of precursor mesa structures on the substrate comprises:

growing an epitaxial layer stack on the substrate, the epitaxial layer stack including:

the layer of the first semiconductor material;

an n + -type layer of the first semiconductor material; and

the layer of the second semiconductor material on the n + -type layer;

electrochemically etching the n + -type layer of the first semiconductor material to form the porous layer;

etching the epitaxial layer stack to form the plurality of precursor mesa structures; and

thermally treating the plurality of precursor mesa structures to cause the layer of the second semiconductor material to relax.

17. The method of claim 16 , wherein:

the layer of the first semiconductor material is n-doped with a doping density less than 1×10 19 cm −3 ;

the n + -type layer of the first semiconductor material has a higher doping density than the layer of the first semiconductor material; and

electrochemically etching the n + -type layer of the first semiconductor material comprises etching the n + -type layer of the first semiconductor material until a difference between a doping density of the n + -type layer and a doping density of the layer of the first semiconductor material is less than 5%.

18. The method of claim 15 , wherein forming the plurality of precursor mesa structures on the substrate comprises:

forming a patterned dielectric layer on the substrate, the patterned dielectric layer including a plurality of apertures to expose portions of a buffer layer on the substrate;

growing, through a respective aperture of the plurality of apertures, a respective epitaxial layer stack on each exposed portion of the exposed portions of the buffer layer on substrate, the respective epitaxial layer stack including:

the layer of the first semiconductor material;

an n + -type layer of the first semiconductor material; and

the layer of the second semiconductor material on the n + -type layer;

electrochemically etching the n + -type layer of the first semiconductor material to form the porous layer; and

thermally treating the plurality of precursor mesa structures to cause the layer of the second semiconductor material to relax.

19. The method of claim 15 , wherein forming the LED layer stack comprises:

forming a growth mask layer on sidewalls of each precursor mesa structure of the plurality of precursor mesa structures;

growing the active region on the layer of the second semiconductor material; and

forming the p-contact layer on the active region.