Scalable high-voltage control circuits using thin film electronics
A device includes a first stage having a first optical switch, a first transistor connected to the first optical switch, and a second transistor connected to the first optical switch and the first transistor. The device also includes a second stage having a second optical switch, a third transistor connected to the second transistor and the second optical switch, and a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.
1. A device, comprising:
a first stage comprising:
a first optical switch;
a first transistor connected to the first optical switch; and
a second transistor connected to the first optical switch and the first transistor, wherein the second transistor comprises a source, a gate, and a drain, wherein the gate of the second transistor is controlled by the first optical switch, and wherein the second transistor comprises:
a thin-film transistor (TFT) with an ungated channel region between the gate and the drain; and
one or more field plates between the gate and the drain; and
a second stage comprising:
a second optical switch;
a third transistor connected to the second transistor and the second optical switch; and
a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.
2. The device of claim 1 , wherein the first optical switch comprises a semiconductor with two terminal contacts, wherein the semiconductor comprises hydrogenated amorphous silicon (a-Si:H), and wherein the terminal contacts form a Schottky barrier to the semiconductor.
3. The device of claim 1 , wherein the first optical switch comprises a semiconductor with two terminal contacts, wherein the semiconductor comprises an organic material, a metal oxide, or a combination thereof.
4. The device of claim 1 , wherein the first and second optical switches and the second and fourth transistors are cascade connected in series to extend an operational voltage range of the device.
5. The device of claim 1 , wherein the device further comprises:
a gate dielectric layer;
an interlevel dielectric (ILD) layer positioned on the gate dielectric layer; and
wherein the second transistor comprises:
a source;
a gate;
a drain;
a first field plate, wherein the gate and the first field plate are positioned at least partially within the gate dielectric layer, and wherein the gate and the first field plate are separated by an ungated channel therebetween;
a channel positioned at least partially within the ILD layer and between the source and the drain, wherein the channel comprises hydrogenated amorphous silicon (a-Si:H); and
a nitride layer positioned at least partially within the ILD layer and between the source and the drain, wherein the nitride layer is positioned at least partially on the channel.
6. The device of claim 5 , wherein the first optical switch comprises:
a second field plate positioned within the gate dielectric layer;
an n+ doped a-Si:H layer positioned at least partially within the ILD layer, wherein the n+ doped a-Si:H layer comprises a first portion, a second portion, and a third portion that are separated from one another; and
a metal layer positioned at least partially within the ILD layer, wherein the metal layer comprises:
a first portion that is positioned at least partially on the first portion of the n+ doped a-Si:H layer;
a second portion that is positioned at least partially on the second portion of the n+ doped a-Si:H layer;
a third portion that is positioned at least partially on the third portion of the n+ doped a-Si:H layer; and
a fourth portion that is positioned at least partially on the second field plate, at least partially between the second and third portions of the n+ doped a-Si:H layer, and at least partially between the second and third portions of the metal layer.
7. The device of claim 5 , wherein the first optical switch comprises:
a metal layer positioned at least partially within the ILD layer, wherein the metal layer comprises a first portion and a second portion, wherein the first and second portions of the metal layer have stepped profiles;
a second channel positioned at least partially within the ILD layer and between the first and second portions of the metal layer, wherein the second channel comprises a-Si:H; and
a second nitride layer positioned at least partially within the ILD layer, at least partially between the first and second portions of the metal layer, and at least partially on the second channel.
8. A device, comprising:
a first stage comprising:
a first optical switch;
a first transistor connected to the first optical switch; and
a second transistor connected to the first optical switch and the first transistor, wherein the first transistor is longer and narrower than the second transistor, wherein the first transistor has a W/L ratio from about 0.1 to about 0.01, and wherein the second transistor is configured to operate at a higher voltage than the first transistor; and
a second stage comprising:
a second optical switch;
a third transistor connected to the second transistor and the second optical switch; and
a fourth transistor connected to the second transistor, the second optical switch, and the third transistor.
9. A switching device for driving an actuator, the switching device comprising:
a first stage comprising:
a first photodiode;
a first transistor comprising a source, a gate, and a drain, wherein the source and the gate of the first transistor are connected to one another, and wherein the drain of the first transistor is connected to the first photodiode; and
a second transistor comprising a source, a gate, and a drain, wherein the source of the second transistor is connected to the source and the gate of the first transistor, wherein the gate of the second transistor is connected to the first photodiode and the drain of the first transistor, and wherein the drain of the second transistor is connected to the first photodiode; and
a second stage comprising:
a second photodiode;
a third transistor comprising a source, a gate, and a drain, wherein the source and the gate of the third transistor are connected to one another and to the drain of the second transistor, and wherein the drain of the third transistor is connected to the second photodiode; and
a fourth transistor comprising a source, a gate, and a drain, wherein the source of the fourth transistor is connected to the drain of the second transistor and to the source and the gate of the third transistor, wherein the gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor, and wherein the drain of the fourth transistor is connected to the second photodiode.
10. The switching device of claim 9 , wherein the first transistor is longer and narrower than the second transistor, and wherein the second transistor is configured to operate at a higher voltage than the first transistor.
11. The switching device of claim 9 , wherein the second transistor comprises a thin-film transistor (TFT), and wherein the gate of the second transistor is controlled by the first photodiode.
12. The switching device of claim 11 , wherein the second transistor further comprises a field plate and an ungated channel region that are positioned between the gate and the drain of the second transistor, and wherein the ungated channel region is positioned between the gate and the field plate of the second transistor.
13. The switching device of claim 9 , wherein the switching device is configured to actuate into an on state in response to a light source causing the first and second photodiodes to induce a photo current, which biases a gate potential of the second and fourth transistors toward a drain voltage.
14. A high-voltage switching device for driving a microelectromechanical systems (MEMS) actuator, the switching device comprising:
a first stage comprising:
a first photodiode comprising a semiconductor with a first terminal contact and a second terminal contact, wherein the semiconductor comprises hydrogenated amorphous silicon (a-Si:H), and wherein the first and second terminal contacts form a Schottky barrier to the semiconductor;
a first transistor comprising a source, a gate, and a drain, wherein the source and the gate of the first transistor are connected to one another, wherein the drain of the first transistor is connected to the first terminal contact of the first photodiode, and wherein the first transistor has a W/L ratio from about 0.1 to about 0.01; and
a second transistor comprising a source, a gate, and a drain, wherein the source of the second transistor is connected to the source and the gate of the first transistor, wherein the gate of the second transistor is connected to the first terminal contact of the first photodiode and the drain of the first transistor, and wherein the drain of the second transistor is connected to the second terminal contact of the first photodiode; and
a second stage comprising:
a second photodiode;
a third transistor comprising a source, a gate, and a drain, wherein the source and the gate of the third transistor are connected to one another and to the drain of the second transistor, and wherein the drain of the third transistor is connected to the second photodiode; and
a fourth transistor comprising a source, a gate, and a drain, wherein the source of the fourth transistor is connected to the drain of the second transistor and to the source and the gate of the third transistor, wherein the gate of the fourth transistor is connected to the second photodiode and the drain of the third transistor, and wherein the drain of the fourth transistor is connected to the second photodiode.
15. The switching device of claim 14 , wherein the first transistor is longer and narrower than the second transistor, and wherein the second transistor is configured to operate at a higher voltage than the first transistor.
16. The switching device of claim 14 , further comprising:
a gate dielectric layer;
an interlevel dielectric (ILD) layer positioned on the gate dielectric layer; and
wherein the second transistor comprises:
a first field plate, wherein the gate and the first field plate of the second transistor are positioned at least partially within the gate dielectric layer, and wherein the gate and the first field plate of the second transistor are separated by an ungated channel therebetween;
a channel positioned at least partially within the ILD layer and between the source and the drain of the second transistor, wherein the channel comprises hydrogenated amorphous silicon (a-Si:H); and
a nitride layer positioned at least partially within the ILD layer and between the source and the drain of the second transistor, wherein the nitride layer is positioned at least partially on the channel.
17. The switching device of claim 16 , wherein the first photodiode comprises:
a second field plate positioned within the gate dielectric layer;
an n+ doped a-Si:H layer positioned at least partially within the ILD layer, wherein the n+ doped a-Si:H layer comprises a first portion, a second portion, and a third portion that are separated from one another; and
a metal layer positioned at least partially within the ILD layer, wherein the metal layer comprises:
a first portion that is positioned at least partially on the first portion of the n+ doped a-Si:H layer;
a second portion that is positioned at least partially on the second portion of the n+ doped a-Si:H layer;
a third portion that is positioned at least partially on the third portion of the n+ doped a-Si:H layer; and
a fourth portion that is positioned at least partially on the second field plate, at least partially between the second and third portions of the n+ doped a-Si:H layer, and at least partially between the second and third portions of the metal layer.
18. The switching device of claim 16 , wherein the first photodiode comprises:
a metal layer positioned at least partially within the ILD layer, wherein the metal layer comprises a first portion and a second portion, wherein the first and second portions of the metal layer have stepped profiles;
a second channel positioned at least partially within the ILD layer and between the first and second portions of the metal layer, wherein the second channel comprises a-Si:H; and
a second nitride layer positioned at least partially within the ILD layer, at least partially between the first and second portions of the metal layer, and at least partially on the second channel.