IP Library Granted Patent US 12,261,687
Granted Patent B2
US 12,261,687 · App. 17/332,285 · Granted Mar 25, 2025

Systems and methods for signal modulation of a plurality of downlink signal representative of a communication signal

Inventors: Jeffrey David Jarriel (San Diego, CA); Daniel Joseph Sutton (San Diego, CA); Matthew James Stoltenberg (San Diego, CA); Brandon Gregory King (San Diego, CA)
Assignee: KRATOS INTEGRAL HOLDINGS, LLC
H04L1/0003H04B7/18506H04L1/0009H04L1/0057H04L67/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,261,687
App. No.
17/332,285
Granted
Mar 25, 2025
Kind
B2
Abstract

Embodiments of systems and methods for modulating a downlink signals representative of a communication signal are provided herein. An example method comprises receiving an input signal; in a first one or more processing blocks in a one or more processors, performing a first modulation operation on first data packets of the input signal based on a modulation scheme for a receiver of the downlink signal; in a second one or more processing blocks in the one or more processors in parallel with the first one or more processing blocks, performing a second modulation operation on second data packets of the input signal based on the modulation scheme; and generating a waveform as the downlink signal based on performing the first and second modulation operations.

Claims (59)

1. A method for modulating a satellite downlink signal representative of a communication signal, the method comprising:

receiving an input signal in the form of a digital bit stream;

splitting the digital bit stream into data packets, each of the data packets including an overlap of data from an adjacent packet;

in a first one or more processing blocks in a one or more processors,

performing a first modulation operation on first data packets of the data packets based on a modulation scheme for a receiver of the downlink signal to create modulated first data packets;

in a second one or more processing blocks in the one or more processors in parallel with performing the first modulation operation in the first one or more processing blocks,

performing a second modulation operation on second data packets of the data packets based on the modulation scheme for the receiver of the downlink signal to create modulated second data packets, wherein the second modulation operation is the same as the first modulation operation;

combining the modulated first data packets and the modulated second data packets in an order which corresponds to the order in which the digital bit stream was received; and

generating a waveform as the downlink signal based on the combined modulated first data packets and the modulated second data packets.

2. The method of claim 1 , wherein the first one or more processing blocks comprises a first one or more central processing unit (CPU) cores and the second one or more processing blocks comprises a second one or more CPU cores.

3. The method of claim 1 , wherein the one or more processors comprises a plurality of processors, wherein the first one or more processing blocks are comprised in a first processor of the plurality and the second one or more processing blocks are comprised in a second processor of the plurality of processors.

4. The method of claim 1 , wherein the one or more processors comprises a single processor comprising the first one or more processing blocks and the second one or more processing blocks.

5. The method of claim 1 , wherein the first one or more processing blocks and the second one or more processing blocks operate in parallel.

6. The method of claim 1 , wherein the first modulation operation comprises a first one or more functions, wherein the first one or more processing blocks comprises a first plurality of processing blocks, wherein at least two of the first one or more functions are performed by the separate processing blocks of the first plurality of processing blocks in parallel.

7. The method of claim 6 , wherein the first one or more functions comprises at least one of:

converting the first data packets to a predetermined format that is based on the modulation scheme;

generating coding corresponding to the modulation scheme;

converting first symbol data of the first data packets to first sample data for the downlink signal;

changing the center frequency of a carrier of the first sample data; and

changing phase and frequency of the first sample data based on the modulation scheme.

8. The method of claim 6 , wherein the second modulation operation comprises a second one or more functions, wherein the second one or more processing blocks comprises a second plurality of processing blocks, wherein at least two of the second one or more functions are performed by the separate processing blocks of the second plurality of processing blocks in parallel.

9. The method of claim 8 , wherein the second one or more functions comprises at least one of:

converting the second data packets to the predetermined format that is based on the modulation scheme;

generating coding corresponding to the modulation scheme;

converting second symbol data of the second data packets to second sample data for the downlink signal;

changing the center frequency of a carrier of the second sample data; and

changing phase and frequency of the second sample data based on the modulation scheme.

10. The method of claim 1 , further comprising:

in a third one or more processing blocks in the one or more processors,

performing a third modulation operation on first outputs from the first and second modulation operation; and

in a fourth one or more processing blocks in the one or more processors in parallel with the third one or more processing blocks,

performing a fourth modulation operation on second outputs from the first and second modulation operation,

wherein the generated waveform is based on performing the third and fourth modulation operations.

11. The method of claim 1 , wherein the one or more processors are one or more general-purpose central processing units (CPU).

12. The method of claim 1 , wherein the one or more processors employ single instructions, multiple data (SIMD) techniques to achieve high throughput.

13. A system for modulating a satellite downlink signal representative of a communication signal, the system comprising:

at least one memory configured to store instructions; and

one or more processors communicatively coupled to the at least one memory, the one or more processors having a plurality of processing blocks and operable to execute the instructions to:

receive an input signal in the form of a digital bit stream;

split the digital bit stream into data packets, each of the data packets including an overlap of data from an adjacent packet;

in a first one or more processing blocks in a one or more processors,

perform a first modulation operation on first data packets of the data packets based on a modulation scheme for a receiver of the downlink signal to create modulated first data packets;

in a second one or more processing blocks in the one or more processors in parallel with performing the first modulation operation in the first one or more processing blocks,

perform a second modulation operation on second data packets of the data packets based on the modulation scheme for the receiver of the downlink signal to create modulated second data packets, wherein the second modulation operation is the same as the first modulation operation;

combining the modulated first data packets and the modulated second data packets in an order which corresponds to the order in which the digital bit stream was received; and

generate a waveform as the downlink signal based on the combined modulated first data packets and the modulated second data packets.

14. The system of claim 13 , wherein the first one or more processing blocks comprises a first one or more central processing unit (CPU) cores and the second one or more processing blocks comprises a second one or more CPU cores.

15. The system of claim 13 , wherein the one or more processors comprises a plurality of processors, wherein the first one or more processing blocks are comprised in a first processor of the plurality and the second one or more processing blocks are comprised in a second processor of the plurality of processors.

16. The system of claim 13 , wherein the one or more processors comprises a single processor comprising the first one or more processing blocks and the second one or more processing blocks.

17. The system of claim 13 , wherein the first one or more processing blocks and the second one or more processing blocks operate in parallel.

18. The system of claim 13 , wherein the one or more processors are one or more general-purpose central processing units (CPU).

19. The system of claim 13 , wherein the one or more processors employ single instructions, multiple data (SIMD) techniques to achieve high throughput.

20. An apparatus for modulating a satellite downlink signal representative of a communication signal, the apparatus comprising:

a means for receiving an input signal in the form of a digital bit stream;

means for splitting the digital bit stream into data packets, each of the data packets including an overlap of data from an adjacent packet;

one or more means for performing a first modulation operation on first data packets of the data packets based on a modulation scheme for a receiver of the downlink signal to create modulated first data packets;

one or more means for performing a second modulation operation on second data packets of the data packets based on the modulation scheme for the receiver of the downlink signal, the one or more means for performing the second modulation operation operated in parallel with performing the first modulation operation in the one or more means for performing the first modulation operation and wherein the second modulation operation is the same as the first modulation operation;

means for combining the modulated first data packets and the modulated second data packets in an order which corresponds to the order in which the digital bit stream was received; and

a means for generating a waveform as the downlink signal based on the combined modulated first data packets and the modulated second data packets.

Assignments (4)
SECURITY INTEREST Recorded Mar 17, 2026
From: FLORIDA TURBINE TECHNOLOGIES INC.; KRATOS ANTENNA SOLUTIONS CORPORATION; KRATOS INTEGRAL HOLDINGS, LLC; KRATOS SRE, INC.; KRATOS TECHNOLOGY & TRAINING SOLUTIONS, INC.; KRATOS UNMANNED AERIAL SYSTEMS, INC.; MICRO SYSTEMS, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 075103/0203 →
RELEASE OF PATENT SECURITY INTEREST RECORDED AT R/F 59664/0917 Recorded Mar 4, 2026
From: TRUIST BANK
To: FLORIDA TURBINE TECHNOLOGIES, INC.; GICHNER SYSTEMS GROUP, INC.; KRATOS ANTENNA SOLUTIONS CORPORATION; KRATOS INTEGRAL HOLDINGS, LLC; KRATOS TECHNOLOGY & TRAINING SOLUTIONS, INC.; KRATOS UNMANNED AERIAL SYSTEMS, INC.; MICRO SYSTEMS, INC.
Reel/Frame 075029/0769 →
SECURITY INTEREST Recorded Apr 6, 2022
From: FLORIDA TURBINE TECHNOLOGIES, INC.; GICHNER SYSTEMS GROUP, INC.; KRATOS ANTENNA SOLUTIONS CORPORATON; KRATOS INTEGRAL HOLDINGS, LLC; KRATOS TECHNOLOGY & TRAINING SOLUTIONS, INC.; KRATOS UNMANNED AERIAL SYSTEMS, INC.; MICRO SYSTEMS, INC.
To: TRUIST BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 059664/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2021
From: JARRIEL, JEFFREY DAVID; SUTTON, DANIEL JOSEPH; STOLTENBERG, MATTHEW JAMES; KING, BRANDON GREGORY
To: KRATOS INTEGRAL HOLDINGS, LLC
Reel/Frame 056374/0423 →
Continuity (2)
Continuation PCTUS2021033905 · May 24, 2021
Related Publication 20220385391A1 · Dec 1, 2022
References Cited (104)
US 5233626A · Ames · 1993 [cited by applicant]
US 5585803A · Miura et al. · 1996 [cited by applicant]
US 6111910A · Cui et al. · 2000 [cited by applicant]
US 6226323B1 · Tan et al. · 2001 [cited by applicant]
US 6542480B1 · Campanella · 2003 [cited by applicant]
US 6781968B1 · Colella et al. · 2004 [cited by applicant]
US 6842495B1 · Jaffe et al. · 2005 [cited by applicant]
US 8953698B2 · Lindoff et al. · 2015 [cited by applicant]
US 9148327B1 · Harris · 2015 [cited by applicant]
US 10177952B1 · Beeler et al. · 2019 [cited by applicant]
US 10541852B2 · Stanciu et al. · 2020 [cited by applicant]
US 10644916B1 · Shattil · 2020 [cited by applicant]
US 10790920B2 · King et al. · 2020 [cited by applicant]
US 11552737B1 · Shattil · 2023 [cited by applicant]
US 20020085648A1 · Burns et al. · 2002 [cited by applicant]
US 20030142726A1 · Eltawil et al. · 2003 [cited by applicant]
US 20030219085A1 · Endres et al. · 2003 [cited by applicant]
US 20040141575A1 · Chen · 2004 [cited by applicant]
US 20040190649A1 · Endres et al. · 2004 [cited by applicant]
US 20040264454A1 · Rajkumar · 2004 [cited by examiner]
US 20050078649A1 · Tehrani et al. · 2005 [cited by applicant]
US 20060034406A1 · Lee · 2006 [cited by applicant]
US 20060291599A1 · Strodtbeck et al. · 2006 [cited by applicant]
US 20070019750A1 · Gaikwad et al. · 2007 [cited by applicant]
US 20070092018A1 · Fonseka et al. · 2007 [cited by applicant]
US 20070297372A1 · Fatemi-Ghomi et al. · 2007 [cited by applicant]
US 20080089458A1 · Wallace et al. · 2008 [cited by applicant]
US 20080109795A1 · Buck · 2008 [cited by examiner]
US 20080159123A1 · Tehrani et al. · 2008 [cited by applicant]
US 20090003493A1 · Gunturi et al. · 2009 [cited by applicant]
US 20090007201A1 · Eerenberg et al. · 2009 [cited by applicant]
US 20090040103A1 · Chansarkar et al. · 2009 [cited by applicant]
US 20090041167A1 · Kadota et al. · 2009 [cited by applicant]
US 20110002366A1 · Michaels et al. · 2011 [cited by applicant]
US 20110026579A1 · Yang · 2011 [cited by applicant]
US 20110129041A1 · Ishihara et al. · 2011 [cited by applicant]
US 20110222584A1 · Michaels · 2011 [cited by applicant]
US 20120069941A1 · Herbig · 2012 [cited by applicant]
US 20120096061A1 · Hauske · 2012 [cited by applicant]
US 20120134511A1 · Vilermo et al. · 2012 [cited by applicant]
US 20120155528A1 · Zhong · 2012 [cited by applicant]
US 20120287886A1 · Fukuoka · 2012 [cited by examiner]
US 20130006601A1 · Mlinarsky et al. · 2013 [cited by applicant]
US 20130115903A1 · Kroeger et al. · 2013 [cited by applicant]
US 20130177115A1 · Yang et al. · 2013 [cited by applicant]
US 20130315346A1 · Varma et al. · 2013 [cited by applicant]
US 20140161210A1 · Chen et al. · 2014 [cited by applicant]
US 20140219374A1 · Pisek · 2014 [cited by applicant]
US 20140273815A1 · Jayasimha · 2014 [cited by applicant]
US 20140321582A1 · Cheng et al. · 2014 [cited by applicant]
US 20150146805A1 · Terry · 2015 [cited by applicant]
US 20150208257A1 · Marini et al. · 2015 [cited by applicant]
US 20170169833A1 · Lecomte · 2017 [cited by examiner]
US 20170353228A1 · Watson et al. · 2017 [cited by applicant]
US 20180069631A1 · Ashrafi · 2018 [cited by applicant]
US 20180198594A1 · Tiirola · 2018 [cited by examiner]
US 20180248676A1 · Raggio et al. · 2018 [cited by applicant]
US 20190372819A1 · Jong et al. · 2019 [cited by applicant]
US 20200028575A1 · Buer et al. · 2020 [cited by applicant]
US 20200132859A1 · Petrovic et al. · 2020 [cited by applicant]
US 20200204281A1 · King et al. · 2020 [cited by applicant]
US 20200313730A1 · Lea et al. · 2020 [cited by applicant]
CN 104424158A · 2015 [cited by applicant]
EP 3537679A1 · 2019 [cited by applicant]
JP 2006332769A · 2006 [cited by applicant]
JP 2014513853A · 2014 [cited by applicant]
JP 2019517078A · 2019 [cited by applicant]
WO 2009154278A1 · 2009 [cited by applicant]
WO 2019243565A1 · 2019 [cited by applicant]
WO 2020131351A1 · 2020 [cited by applicant]
Notice of Allowance dated May 4, 2022 in U.S. Appl. No. 17/031,507. [cited by applicant]
Office Action dated Jul. 17, 2023 in U.S. Appl. No. 17/332,349. [cited by applicant]
Notice of Allowance dated Aug. 28, 2023 in U.S. Appl. No. 17/332,349. [cited by applicant]
International Search Report and Written Opinion for corresponding application No. PCT/US2021/033867 mailed on Feb. 14, 2022, in 11 pages. [cited by applicant]
International Search Report and Written Opinion for corresponding application No. PCT/US2021/033875 mailed on Feb. 14, 2022, in 14 pages. [cited by applicant]
Zhou. “Efficient Clock and Carrier Recovery Algorithms for Single-Carrier Coherent Optical Systems: A systematic review on challenges and recent progress.” Feb. 19, 2014. IEEE, IEEE Signal Processing Magazine. 31(2):35-… [cited by applicant]
Barros et al. “A Soft-Handover Scheme for LEO Satellite Networks.” IEEE 78th Vehicular Technology Conference, Sep. 2, 2013, pp. 1-5. [cited by applicant]
Callaghan et al. “An investigation of site diversity and comparison with ITU-R recommendations.” Radio Science. vol. 43, No. 4. Aug. 1, 2008. 8 pages. [cited by applicant]
International Search Report and Written Opinion for corresponding application No. PCT/US2019/064183, mailed on Mar. 12, 2020, in 13 pages. [cited by applicant]
International Search Report and Written Opinion for corresponding application No. PCT/US2020/065351, mailed on Apr. 23, 2021, in 16 pages. [cited by applicant]
International Search Report and Written Opinion for corresponding application No. PCT/US2020/065358 mailed on Apr. 21, 2021, in 15 pages. [cited by applicant]
International Search Report and Written Opinion of PCT/US2021/033905 dated Apr. 4, 2022. 15 pages. [cited by applicant]
Thread_Block_2021 (Thread block (CUDA programming, downloaded from Wikipedia archive data Mar. 3, 2021). Year: 2021. [cited by applicant]
Office Action dated May 29, 2024 in U.S. Appl. No. 17/332,675. [cited by applicant]
Office Action dated Jul. 30, 2024 in Japanese Patent Application No. 2022-535769. [cited by applicant]
Faulkner et al., A reconfigurable wideband streaming channeliser for RF sensing applications: A multiple GPU-based implementation [online], 2017 11th International Conference on Signal Processing and Communication Syste… [cited by applicant]
Faulkner et al., GPU Synthesis of RF Channeliser Outputs for a Variable Bandwidth Microwave Digital Receiver, 2018 12th International Conference on Signal Processing and Communication Systems (ICSPCS), Feb. 3, 2019. [cited by applicant]
Notice of Allowance dated Sep. 25, 2024 in U.S. Appl. No. 17/785,346. [cited by applicant]
Office Action dated Oct. 10, 2024 in U.S. Appl. No. 17/332,675. [cited by applicant]
D. C. Dinis, R. F. Cordeiro, A. S. R. Oliveira, J. Vieira and T. O. Silva, “A Fully Parallel Architecture for Designing Frequency-Agile and Real-Time Reconfigurable FPGA-Based RF Digital Transmitters,” in IEEE Transacti… [cited by applicant]
P. Aviely, O. Radovsky and R. Ginosar, “DVB-S2 software defined radio modem on the RC64 manycore DSP,” 2016 IEEE Aerospace Conference, Big Sky, Mt, USA, 2016, pp. 1-10. [cited by applicant]
D. C. Dinis et al., “A Real-Time Architecture for Agile and FPGA-Based Concurrent Triple-Band All-Digital RF Transmission,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, No. 11, pp. 4955-4966, Nov. 2… [cited by applicant]
Office Action dated Dec. 17, 2024 in Japanese Patent Application No. 2023-566724 (9 pages). [cited by applicant]
Office Action dated Jan. 21, 2025 in U.S. Appl. No. 17/332,675 (22 pages). [cited by applicant]
Office Action dated Jan. 21, 2025 in Japanese Patent Application No. 2022-536588 (5 pages). [cited by applicant]
Carrasco-Alvarez 2015 (A Fading Channel Simulator Implementation Based on GPU Computing Techniques, Hindawi Publishing Corporation Mathematical Problems in Engineering vol. 2015, Article ID 237061) (Year: 2015). [cited by applicant]
Anupama 2013 (Modeling Noisy and Fading Channels, International Journal of Engineering and Innovation Technology (IJETT) vol. 2, Issue 3, Sep. 2012). (Year: 2012) 4 pages. [cited by applicant]
Lisong 2013 (A practical simulation method for generating phase noise of oscillators, 2013 2nd International Conference on Measurement, Information and Control) (Year: 2013). [cited by applicant]
Gharaibeh 2012 (Nonlinear Distortion in Wireless Systems: Modeling and Simulation with Matlab, ISBN 9780470661048 2012). ( Year: 2012). [cited by applicant]
Office Action dated Nov. 26, 2024 in Japanese Patent Application No. 2023-562734. [cited by applicant]
D. C. Dinis et al., “A Fully Parallel Architecture for Designing Frequency-Agile and Real-Time Reconfigurable FPGA-Based RF Digital Transmitters,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, No. 3,… [cited by applicant]
P. Aviely et al., “DVB-S2 software defined radio modem on the RC64 manycore DSP,” 2016 IEEE Aerospace Conference, Big Sky, MT, USA, 2016, pp. 1-10. [cited by applicant]
D. C. Dinis et al., “A Real-Time Architecture for Agile and FPGA-Based Concurrent Triple-Band All-Digital RF Transmission,” in IEEE Transactions on Microwave Theory and Techniques, vol. 66, No. 11, pp. 4955-4966, Nov. 2… [cited by applicant]
Notice of Allowance dated Jan. 22, 2025 in U.S. Appl. No. 17/785,298. [cited by applicant]