IP Library Granted Patent US 11,513,301
Granted Patent B2
US 11,513,301 · App. 17/351,546 · Granted Nov 29, 2022

Chip-scale optoelectronic transceiver having microsprings on an interposer substrate

Inventor: Christopher L. Chua (San Jose, CA)
Assignee: Palo Alto Research Center Incorporated
G02B6/4278G02B6/423G02B6/4246H01L23/49811H01L31/12H04B10/25H04B10/40
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,513,301
App. No.
17/351,546
Granted
Nov 29, 2022
Kind
B2
Abstract

A chip-scale transceiver includes an interposer having microspring electrical contacts disposed on the interposer substrate. At least one electronic chip and at least one optoelectronic chip are electrically coupled to the interposer through the microsprings. The electronic chip includes at least one of an amplifier array and a laser driver array. First electrical contact pads arranged to make electrical contact with the first microsprings of the interposer. The optoelectronic chip includes at least one of a laser array and a photodetector array. Second electrical contact pads arranged to make electrical contact with the second microsprings of the interposer are disposed on the optoelectronic chip substrate. The transceiver has an area less than or equal to 0.17 mm 2 per Gbps.

Claims (66)

1. A transceiver, comprising:

an interposer comprising:

an interposer substrate; and

first and second microspring electrical contacts disposed on the interposer substrate;

at least one electronic chip comprising:

an electronic chip substrate comprising an array of electronic devices; and

first electrical contact pads disposed on the electronic chip substrate, the first electrical contact pads arranged to make electrical contact with the first microsprings of the interposer; and

at least one optoelectronic chip, comprising:

an optoelectronic chip substrate comprising an array of optoelectronic devices; and

second electrical contact pads disposed on the optoelectronic chip substrate, the second electrical contact pads arranged to make electrical contact with the second microsprings of the interposer.

2. The transceiver of claim 1 , wherein:

the electronic devices comprise at least one of an amplifier array and a laser driver array; and

the optoelectronic devices comprise at least one of a laser array and a photodetector array.

3. The transceiver of claim 1 , wherein the optoelectronic devices comprise an array of vertical cavity surface emitting lasers (VCSELs).

4. The transceiver of claim 1 , wherein the at least one optoelectronic chip comprises:

an optoelectronic receiver chip that includes an array of photodetectors; and

an optoelectronic transmitter chip that includes an array of vertical cavity surface emitting lasers (VCSELs).

5. The transceiver of claim 1 , wherein:

the electronic chip substrate comprises a first material; and

the optoelectronic chip substrate comprises a second material different from the first material.

6. The transceiver of claim 1 , wherein the transceiver is configured to operate a plurality of communication lanes, each communication lane configured to operate at greater than or equal to 25 Gbps.

7. The transceiver of claim 1 , wherein the transceiver operates at less than or equal to about 10 pJ per bit.

8. The transceiver of claim 1 , wherein the transceiver operates at less than or equal to about 1 pJ per bit.

9. The transceiver of claim 1 , wherein the transceiver has an area less than or equal to 0.17 mm 2 per Gbps.

10. The transceiver of claim 1 , further comprising holes through the interposer substrate that are aligned with the optoelectronic devices, the holes configured to receive and align optical fibers such that the optical fibers are optically coupled to the optoelectronic devices.

11. The transceiver of claim 1 , wherein a volume of the transceiver is less than or equal to 10×8×5 mm 3 .

12. The transceiver of claim 1 , wherein the interposer substrate comprises silicon, a singulated portion of a silicon wafer, glass, or FR4.

13. The transceiver of claim 1 , wherein:

the interposer comprises contact pads arranged along at least one edge of the interposer; and

the edge contact pads have a bandwidth density of greater than 1 Tbps per cm.

14. The transceiver of claim 1 , wherein the optoelectronics module further includes microlenses disposed between at least some of the optoelectronics components and the optical fibers.

15. A communication system comprising:

a transceiver, comprising:

an interposer comprising:

an interposer substrate; and

first and second microspring electrical contacts disposed on the interposer substrate;

at least one electronic chip comprising:

an electronic chip substrate comprising an array of electronic devices; and

first electrical contact pads disposed on the electronic chip substrate, the first electrical contact pads arranged to make electrical contact with the first microsprings of the interposer; and

at least one optoelectronic chip, comprising:

an optoelectronic chip substrate comprising an array of optoelectronic devices; and

second electrical contact pads disposed on the optoelectronic chip substrate, the second electrical contact pads arranged to make electrical contact with the second microsprings of the interposer;

a network interface device configured to control operation of the transceiver; and

a mother board comprising:

a first connector configured to electrically connect to the transceiver; and

a second connector configured to electrically connect to the network interface device, the motherboard having electrical traces configured to electrically connect the network interface device to the transceiver.

16. The system of claim 15 , wherein the transceiver is located less than 5 cm from the network interface device.

17. The system of claim 15 , wherein the transceiver operates at less than or equal to about 1 pJ per bit.

18. The system of claim 15 , wherein a volume of the transceiver is less than or equal to 10×8×5 mm 3 .

19. The system of claim 15 , wherein the transceiver has an area less than or equal to 0.17 mm 2 per Gbps.

20. The system of claim 15 , wherein the transceiver is configured to operate a plurality of communication lanes, each communication lane configured to operate at greater than or equal to 25 Gbps.

21. A method of making a transceiver, comprising:

forming multiple interposers on an interposer wafer, each interposer comprising first and second stress-engineered microspring electrical contacts disposed on a surface of the interposer wafer;

forming at least one electronic chip comprising:

fabricating electronic devices in and/or on a surface of an electronic chip substrate; and

fabricating first electrical contact pads on the electronic chip substrate, the first electrical contact pads arranged to make electrical contact with the first microsprings of the interposer;

forming at least one optoelectronic chip, comprising:

fabricating optoelectronic devices in and/or on a surface of an optoelectronic chip substrate; and

fabricating second electrical contact pads on the electronic chip substrate, the second electrical contact pads arranged to make electrical contact with the first microsprings of the interposer.

22. The method of claim 21 , wherein:

the electronic devices comprise at least one of an amplifier array and a laser driver array; and

the optoelectronic devices comprise at least one of a laser array and a photodetector array.

23. The method of claim 21 , wherein forming the at least one optoelectronic chip comprises:

fabricating an optoelectronic receiver chip comprising the array of photodetectors; and

fabricating an optoelectronic transmitter chip comprising the array of lasers.

24. The method of claim 21 , wherein the transceiver has an area less than or equal to 0.17 mm 2 per Gbps.

Assignments (8)
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
Continuity (2)
Continuation 16815932 · Mar 11, 2020
Related Publication 20210311271A1 · Oct 7, 2021