Systems and methods for processing variable coding and modulation (VCM) based communication signals using feedforward carrier and timing recovery

1. A method for processing a digital bit stream, wherein the digital bit stream is a digitized communication signal, the method comprising:

dividing, at one or more processors, the digital bit stream into a plurality of data packets;

in a first processing block of the one or more processors,

performing a carrier recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the first portion of the plurality of data packets, and

performing a carrier recovery operation on the first portion of the plurality of data packets;

in a second processing block of the one or more processors, in parallel with the process of performing the carrier recovery error calculation and the carrier recovery operation on the first portion of the plurality of data packets,

performing the carrier recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the second portion of the plurality of data packets, and

performing the carrier recovery operation on the second portion of the plurality of data packets; and

combining the first portion of the plurality of data packets and the second portion of the plurality of data packets based on phase stitching.

2. The method of claim 1 , further comprising:

in a third processing block of the one or more processors,

performing a timing recovery error calculation on the first portion of the plurality of data packets, and

performing a timing recovery operation on the first portion of the plurality of data packets; and

in a fourth processing block of the one or more processors, in parallel with the process of performing the timing recovery error calculation and the timing recovery operation on the first portion of the plurality of data packets,

performing the timing recovery error calculation on the second portion of the plurality of data packets, and

performing the timing recovery operation on the second portion of the plurality of data packets.

3. The method of claim 2 , wherein performing the timing recovery error calculation on the first portion of the plurality of data packets and on the second portion of the plurality of data packets comprises preforming a second PLL function on the decimated data of the first and second portions of the plurality of data packets.

4. The method of claim 2 , wherein performing the timing recovery error calculation on the first portion of the plurality of data packets and on the second portion of the plurality of data packets comprises:

receiving the plurality of data packets as samples of a downlink signal, the samples having an unknown symbol rate and frequency;

determining a timing error of the samples based on an estimate of the unknown symbol rate;

decimating the samples by a decimation filter;

executing a second PLL function on the decimated data of the first and second portions of the plurality of data packets to determine a phase, frequency, and Doppler rate of the samples; and

updating the estimate of the unknown symbol rate.

5. The method of claim 4 , wherein each of the plurality of data packets includes an overlap of data from an adjacent data packet, and wherein the second PLL function is a second order PLL.

6. The method of claim 4 , wherein the plurality of data packets are framed data packets, and wherein the second PLL function is one of a reversable PLL and a reversable, iterative PLL.

7. The method of claim 4 , wherein performing the carrier recovery error calculation on the first portion of the plurality of data packets and on the second portion of the plurality of data packets comprises:

receiving the samples associated with synchronized samples of the downlink signal;

determining a carrier error of the samples based on an estimate of a frequency of the downlink signal and a product of the samples raised to a power of n, wherein n is an integer;

decimating the samples by the decimation filter;

executing the first PLL function on the decimated samples to determine a phase, frequency, and Doppler rate of the samples; and

updating the estimate of the frequency of the downlink signal.

8. The method of claim 2 , further comprising:

combining the output of the third processing block and the output of the fourth processing block into blocks of time corrected symbols; and

locating frame boundaries of the blocks of time corrected symbols by detecting a frame marker,

wherein performing the carrier recovery error calculation on the first and second portions of the plurality of data packets is based on the located frame boundaries.

9. The method of claim 1 , wherein the first PLL function is one of a second order PLL, a third order PLL, a reversable PLL, and a reversable, iterative PLL.

10. The method of claim 1 , wherein the first processing block and the second processing block comprise a plurality of central processing unit (CPU) cores.

11. The method of claim 1 , wherein the one or more processors employ single instructions, multiple data (SIMD) techniques to achieve high throughput.

12. The method of claim 1 , wherein the one or more processors are one or more general-purpose central processing units (CPUs), the first processing block comprises a first one or more CPU cores of the one or more general-purpose CPUs, and the second processing block comprises a second one or more CPU cores of the one or more general-purpose CPUs.

13. A method for processing a digital bit stream, wherein the digital bit stream is a frame based digitized communication signal, the method comprising:

dividing, at one or more processors, the digital bit stream into a plurality of data packets;

in a first processing block of the one or more processors,

performing a timing recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the first portion of the plurality of data packets, and

performing a timing recovery operation on the first portion of the plurality of data packets;

in a second processing block of the one or more processors, in parallel with the process of performing the timing recovery error calculation and the timing recovery operation on the first portion of the plurality of data packets,

performing the timing recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the second portion of the plurality of data packets, and

performing the timing recovery operation on the second portion of the plurality of data packets;

combining the output of the first processing block and the output of the second processing block into combined processing blocks of time corrected symbols including one or more frame markers;

searching the combined processing blocks of the time corrected symbols for the one or more frame markers included with each combined processing block of the time corrected symbols;

executing a correlator process and a frequency tracking process to locate frame boundaries and track a carrier frequency; and

outputting frames of the time corrected symbols.

14. The method of claim 13 , wherein executing the correlator process and the frequency tracking process comprises:

performing a frequency lock loop (FLL) function to compare a phase difference between two adjacent frame markers.

15. The method of claim 14 , wherein performing the FLL function to compare the phase difference between the two adjacent frame markers comprises

calculating arctan(A*conj(B))/(2*pi)*FR to obtain a calculated value, where A is an IQ value of a previous collapsed frame marker, B is an IQ value of a current collapsed frame marker and FR is an update rate of a frame marker.

16. The method of claim 15 , further comprising dividing, at the one or more processors, the frames of the time corrected symbols into a plurality of time corrected symbols;

in a third processing block of the one or more processors,

performing a carrier recovery error calculation on the first portion of the plurality of data packets, comprising preforming a second phase locked loop PLL function on decimated data of a first portion of the plurality of time corrected symbols, and

performing a carrier recovery operation on the first portion of the plurality of time corrected symbols;

in a fourth processing block of the one or more processors, in parallel with the process of performing the carrier recovery error calculation on the first portion of the plurality of data packets and performing the carrier recovery operation on the first portion of the plurality of time corrected symbols,

performing the carrier recovery error calculation on a second portion of the plurality of time corrected symbols, comprising preforming the second PLL function on decimated data of the second portion of the plurality of time corrected symbols, and

performing the carrier recovery operation on the second portion of the plurality of time corrected symbols; and

combining the first portion of the plurality of time corrected symbols and the second portion of the plurality of time corrected symbols based on phase stitching.

17. The method of claim 16 , further comprising adding the second PLL function after the FLL function to enhance tracking and provide an improved phase, Doppler and Doppler estimate for the carrier recovery error calculation.

18. The method of claim 13 , wherein the one or more processors are one or more general-purpose central processing units (CPUs), the first processing block comprises a first one or more CPU cores of the one or more general-purpose CPUs, and the second processing block comprises a second one or more CPU cores of the one or more general-purpose CPUs.

19. A method for processing a digital bit stream, wherein the digital bit stream is a frame based digitized communication signal, the method comprising:

dividing, at one or more processors, the digital bit stream into a plurality of data packets;

in a first processing block of the one or more processors,

performing a timing recovery error calculation on a first portion of the plurality of data packets, comprising preforming a first phase locked loop (PLL) function on decimated data of the first portion of the plurality of data packets, and

performing a timing recovery operation on the first portion of the plurality of data packets; and

in a second processing block of the one or more processors, in parallel with the process of performing the timing recovery error calculation and the timing recovery operation on of the first portion on the plurality of data packets,

performing the timing recovery error calculation on a second portion of the plurality of data packets, comprising preforming the first PLL function on decimated data of the second portion of the plurality of data packets, and

performing the timing recovery operation on the second portion of the plurality of data packets.

20. The method of claim 19 , further comprising:

combining the output of the first processing block and the output of the second processing block into combined processing blocks of time corrected symbols including one or more frame markers; and

locating frame boundaries of each of the combined processing blocks of the time corrected symbols by detecting a frame marker.

21. The method of claim 20 , wherein locating the frame boundaries includes:

executing a correlator process and a frequency tracking process to locate the frame boundaries and track a carrier frequency; and

outputting frames of the time corrected symbols.

22. A system for processing the digital bit stream representative of the frame based digitized communication signal, the system comprising:

a digitizer configured to convert a received analog signal into the digital bit stream; and

the one or more processors communicatively coupled to the digitizer, the one or more processors including the first processing block and the second processing block and configured to perform the method of claim 19 .

23. The method of claim 19 , wherein the one or more processors are one or more general-purpose central processing units (CPUs), the first processing block comprises a first one or more CPU cores of the one or more general-purpose CPUs, and the second processing block comprises a second one or more CPU cores of the one or more general-purpose CPUs.