Fabricating a coil above and below a magnetoresistance element

1. A method, comprising:

forming a metal layer on a substrate, wherein the metal layer comprises a first coil;

forming a planarized insulator layer on the metal layer,

forming at least one via in the planarized insulator layer;

depositing a magnetoresistance (MR) element on the planarized insulator layer, wherein the at least one via electrically connects to the metal layer on one end and to MR element on the other end; and

forming a second coil extending above the MR element.

2. The method of claim 1 , wherein the first coil and the second coil are the same coil.

3. The method of claim 1 , further comprising depositing a hard mask directly on the metal layer,

wherein forming the at least one via in the planarized insulator layer comprises forming the at least one via in the planarized insulator layer and in the hard mask.

4. The method of claim 3 , wherein depositing the hard mask comprises depositing a hard mask comprising silicon dioxide.

5. The method of claim 1 , further comprising depositing insulator material directly on the metal layer.

6. The method of claim 5 , wherein depositing the insulator material directly on the metal layer comprises using high-density plasma chemical vapor deposition (HDP-CVD).

7. The method of claim 5 , wherein forming a planarized insulator layer on the metal layer comprises forming a planarized insulator layer on the coil on the insulator material.

8. The method of claim 1 , wherein depositing the MR element comprises depositing at least one of a tunneling magnetoresistance (TMR), a magnetic tunnel junction (MTJ) and/or a giant magnetoresistance (GMR).

9. The method of claim 1 , wherein depositing the MR element comprises depositing an MR stack or MR pillar.

10. The method of claim 1 , further comprising depositing a hard mask directly on to the MR element.

11. The method of claim 1 , wherein the substrate is a dielectric, and further comprising:

covering an integrated circuit (IC) with the dielectric;

forming at least one via in the dielectric,

wherein the at least one via in the dielectric electrically connects the metal layer to the IC.

12. A magnetic field sensor, comprising:

a substrate;

a metal layer on the substrate and comprising a first coil;

a planarized insulator layer on the metal layer;

a magnetoresistance (MR) element on the planarized insulator layer;

at least one via in the planarized insulator layer that electrically connects to the metal layer on one end and to the MR element at the other end; and

a second coil extending above the MR element.

13. The magnetic field sensor of claim 12 , wherein the first coil and the second coil are the same coil.

14. The magnetic field sensor of claim 12 , further comprising a hard mask directly on the metal layer,

wherein the at least one via is in the planarized insulator layer and in the hard mask.

15. The magnetic field sensor of claim 14 , the hard mask comprises silicon dioxide.

16. The magnetic field sensor of claim 12 , further comprising an insulator material located directly on the metal layer.

17. The magnetic field sensor of claim 12 , wherein the MR element comprises at least one of a tunneling magnetoresistance (TMR), a magnetic tunnel junction (MTJ) and/or a giant magnetoresistance (GMR).

18. The magnetic field sensor of claim 12 , wherein the MR element comprises an MR stack or MR pillar.

19. The magnetic field sensor of claim 12 , further comprising a hard mask directly on to the MR element.

20. The magnetic field sensor of claim 12 , wherein the substrate is a dielectric.

21. The magnetic field sensor of claim 20 , further comprising an integrated circuit (IC),

wherein the dielectric covers the IC.

22. The magnetic field sensor of claim 12 , further comprising at least one via in the dielectric,

wherein the at least one via in the dielectric electrically connects the metal layer to the IC.