Semiconductor device to reduce signal loss in a transmission line
A semiconductor device that includes an epitaxial layer having a first-type dopant, a first well having a second-type dopant, a base layer having the second-type dopant, a first metal layer comprising a first base terminal and an inner conductor, and a first via connecting the first base terminal to the first well. The base layer is formed within the epitaxial layer and in contact with the first well and at least one dielectric separates the inner conductor from the first base terminal, and the base layer.
1. A semiconductor device comprising:
an epitaxial layer having a first-type dopant;
a first well having a second-type dopant;
a base layer having the second-type dopant, the base layer formed within the epitaxial layer and in contact with the first well;
a first metal layer comprising a first base terminal and an inner conductor;
a first via connecting the first base terminal to the first well;
an isolation layer on the epitaxial layer;
a polysilicon region on the isolation layer; and
a second via connecting the first base terminal to the polysilicon region,
wherein at least one dielectric separates the inner conductor from the first base terminal, and the base layer.
2. The semiconductor device of claim 1 , wherein, in operation, a voltage is applied to the inner conductor forming a depleted region in the base layer.
3. The semiconductor device of claim 1 , further comprising:
a second well having the second-type dopant;
a second base terminal; and
a second via connecting the second base terminal to the second well,
wherein the base layer is between, and in contact with, the first well and the second well,
wherein the first metal layer further comprises the second base terminal, and
wherein the at least one dielectric separates the inner conductor from the first base terminal, the second base terminal and the base layer.
4. The semiconductor device of claim 3 , wherein the first metal layer further comprises a first metal portion, and further comprising:
a first plug having the first-type dopant, the first plug formed in the epitaxial layer;
a second metal layer;
a first plurality of vias connecting the first metal portion of the first metal layer to the first plug; and
a second plurality of vias connecting the first metal portion of the first metal layer to the second metal layer.
5. The semiconductor device of claim 4 , wherein the first metal layer further comprises a second metal portion, and further comprising:
a second plug having the first-type dopant, the second plug formed in the epitaxial layer;
a third plurality of vias connecting the second metal portion of the first metal layer to the second plug; and
a fourth plurality of vias connecting the second metal portion of the first metal layer to the second metal layer.
6. The semiconductor device of claim 5 , further comprising a silicon substrate having a second-type dopant,
wherein the epitaxial layer is in contact with the substrate.
7. The semiconductor device of claim 6 , further comprising a buried layer having a first-type dopant,
wherein the buried layer is in contact with the substrate, the first plug and the second plug.
8. The semiconductor device of claim 1 , wherein the first-type dopant is a n-type dopant, and
wherein the second-type dopant is an p-type dopant.
9. The semiconductor device of claim 8 , wherein, in operation, a negative voltage is applied to the inner conductor to form a depleted region in the base layer.
10. A semiconductor device comprising:
an epitaxial layer having a first-type dopant;
a first well having a second-type dopant;
a base layer having the second-type dopant, the base layer formed within the epitaxial layer and in contact with the first well;
a first metal layer comprising a first base terminal and an inner conductor;
a first via connecting the first base terminal to the first well,
wherein at least one dielectric separates the inner conductor from the first base terminal, and the base layer, and further including:
an isolation layer on the epitaxial layer, the isolation layer comprising a first portion and a second portion;
a first polysilicon region on the first portion of the isolation layer;
a second polysilicon region on the second portion of the isolation layer;
a third via connecting the first base terminal to the first polysilicon region; and
a fourth via connecting the second base terminal to the second polysilicon region.
11. The semiconductor device of claim 10 , further comprising:
an isolation layer on the epitaxial layer;
a polysilicon region on the isolation layer; and
a second via connecting the first base terminal to the polysilicon region.
12. The semiconductor device of claim 10 , further comprising:
a second well having the second-type dopant;
a second base terminal; and
a second via connecting the second base terminal to the second well,
wherein the base layer is between, and in contact with, the first well and the second well,
wherein the first metal layer further comprises the second base terminal, and
wherein the at least one dielectric separates the inner conductor from the first base terminal, the second base terminal and the base layer.
13. The semiconductor device of claim 12 , wherein the first metal layer further comprises a first metal portion, and further comprising:
a first plug having the first-type dopant, the first plug formed in the epitaxial layer;
a second metal layer;
a first plurality of vias connecting the first metal portion of the first metal layer to the first plug; and
a second plurality of vias connecting the first metal portion of the first metal layer to the second metal layer.
14. The semiconductor device of claim 13 , wherein the first metal layer further comprises a second metal portion, and further comprising:
a second plug having the first-type dopant, the second plug formed in the epitaxial layer;
a third plurality of vias connecting the second metal portion of the first metal layer to the second plug; and
a fourth plurality of vias connecting the second metal portion of the first metal layer to the second metal layer.
15. The semiconductor device of claim 14 , further comprising a silicon substrate having a second-type dopant,
wherein the epitaxial layer is in contact with the substrate.
16. The semiconductor device of claim 15 , further comprising a buried layer having a first-type dopant,
wherein the buried layer is in contact with the substrate, the first plug and the second plug.
17. A method comprising:
reducing losses in a transmission line losses in a semiconductor device, wherein the semiconductor device comprises:
an epitaxial layer having a first-type dopant;
a first well having a second-type dopant;
a base layer having the second-type dopant, the base layer formed within the epitaxial layer and in contact with the first well;
a first metal layer comprising a first base terminal and an inner conductor;
a first via connecting the first base terminal to the first well, and
wherein at least one dielectric separates the inner conductor from the first base terminal, and the base layer; and
wherein shielding the transmission line comprises applying a bias to the first base terminal, and wherein the semiconductor device further includes:
an isolation layer on the epitaxial layer;
a polysilicon region on the isolation layer; and
a second via connecting the first base terminal to the polysilicon region.
18. The method of claim 17 , wherein applying a bias to the first base terminal comprises applying a negative voltage or a positive voltage to the first base terminal.
19. The method of claim 17 , wherein applying a bias to the first base terminal forms a depletion region in the base layer.
20. The semiconductor device of claim 10 , wherein, in operation, a voltage is applied to the inner conductor forming a depleted region in the base layer.
21. The semiconductor device of claim 10 , wherein the first-type dopant is a n-type dopant, and
wherein the second-type dopant is an p-type dopant.
22. The semiconductor device of claim 21 , wherein, in operation, a negative voltage is applied to the inner conductor to form a depleted region in the base layer.