Double-diffused metal-oxide-semiconductor transistor including a recessed dielectric
In one aspect, a double-diffused metal oxide semiconductor (DMOS) includes a region of a semiconductor having a first region of a semiconductor having a first-type dopant, a first well having a second-type dopant, a dielectric within the first well, the dielectric having a bottom surface and a top surface opposite the bottom surface, a gate disposed on the top surface of the dielectric. The gate, the dielectric and the first well are configured to form a first reduced surface field (RESURF). The bottom surface of the dielectric has a first portion and a second portion, and the first portion of the bottom surface of the dielectric is closer to the top surface of the dielectric than the second portion of the bottom surface of the dielectric.
1. A method comprising:
forming a double-diffused metal oxide semiconductor (DMOS) comprising:
depositing a first silicon nitride on a well;
depositing a first photoresist on the first silicon nitride;
using a first photolithographic process to remove portions of the first photoresist to expose at least one portion of the first silicon nitride;
performing a first etching of the first silicon nitride and the well;
depositing a first dielectric on a portion of the well etched by the first etching;
removing the first silicon nitride;
depositing a second silicon nitride on the well and an epitaxial layer;
depositing a second photoresist on the second silicon nitride;
using a second photolithographic process to remove portions of the second photoresist to expose at least one portion of the second silicon nitride;
performing a second etching of the second silicon nitride, the well, and the epitaxial layer; and
depositing a second dielectric on a portion of the well and the epitaxial layer etched by the second etching, wherein the second dielectric is in direct contact with the first dielectric.
2. The method of claim 1 , further comprising performing a chemical-mechanical polishing (CMP) on the first dielectric.
3. The method of claim 2 , further comprising performing CMP on the second dielectric.
4. The method of claim 1 , wherein depositing the first dielectric comprises depositing a first layer of silicon dioxide.
5. The method of claim 4 , wherein depositing the first dielectric comprises depositing the first dielectric using high-density-plasma (HDP) Chemical Vapor Deposition (CVD).
6. The method of claim 5 , wherein depositing the second dielectric comprises depositing a second layer of silicon dioxide,
wherein depositing the second dielectric comprises depositing the second dielectric using HDPCVD.
7. The method of claim 6 , wherein depositing the second layer of silicon dioxide comprises depositing a second layer of silicon dioxide that is thinner than the first layer of silicon dioxide.
8. The method of claim 7 , wherein the first layer has a thickness of about 6,000 Angstroms, and
wherein the second layer has a thickness of about 4,000 Angstroms.
9. The method of claim 8 , further comprising depositing an oxide layer of about 200 Angstroms on the silicon substrate before depositing the first silicon nitride.
10. The method of claim 1 , further comprising depositing an oxide on the silicon substrate before depositing the first silicon nitride.