Configurable variable-length shift register circuits
Configurable variable-length shift register circuits include a group of flip-flops connected in a serial configuration. The plurality of flip-flops is connected to a serial data-in line and a clock line. Each flip-flop can include a data input, a clock input configured to receive a clock signal from the clock line, and a data output. The plurality of flip-flops can include a serial data-out line. The circuit includes a plurality of multiplexers connected to the plurality of flip-flops to enable a desired number of flip-flops for an application. A nonvolatile memory can be connected to the plurality of multiplexers and configured to receive a register-length indication, where the register-length indication corresponds to a selected number of flip-flops selected for enablement for a given application.
1. A configurable variable-length shift register circuit for adjusting an output data format to a desired bit-length for data communication, the circuit comprising:
a plurality of flip-flops connected in a serial configuration, wherein the plurality of flip-flops is connected to a serial-in line and a clock line, wherein in each flip-flop includes a data input, a clock input configured to receive a clock signal from the clock line, and a data output, and wherein the plurality of flip-flops includes a serial-out line;
a plurality of multiplexers connected to the plurality of flip-flops, wherein each multiplexer includes first and second data inputs and a control input, wherein one of the first and second data inputs is connected to the serial-in line, wherein the control input selects between the data inputs, and wherein each multiplexer includes an output connected to the input of a respective flip-flop;
a nonvolatile memory connected to the plurality of multiplexers and configured to receive a register-length indication, wherein the register-length indication corresponds to a selected number of flip-flops selected for enablement; and
a programming interface connected to the nonvolatile memory and configured to allow a user to input the register-length indication;
wherein the nonvolatile memory is operative to configure the plurality of multiplexers to enable a plurality of enabled flip-flops corresponding in number to the register-length indication, and
wherein the plurality of enabled flip-flops of the variable-length shift register is configured to produce a data output with an output data format having a desired bit-length corresponding to the number of enabled flip-flops.
2. The circuit of claim 1 , further comprising an interface driver configured to communicate with the plurality of flip-flops and one or more device registers, wherein the interface driver is connected to the output of each flip-flop, and wherein the interface driver is configured to move data between the plurality of flip-flops and the one or more device registers.
3. The circuit of claim 2 , wherein the interface driver comprises a serial interface.
4. The circuit of claim 3 , wherein the serial interface comprises a serial-peripheral interface (SPI).
5. The circuit of claim 3 , wherein the serial interface comprises a universal asynchronous receiver/transmitter (UART) interface.
6. The circuit of claim 3 , wherein the serial interface comprises universal an I2C interface.
7. The circuit of claim 2 , wherein each of the flips-flops of the plurality of flip-flops includes a set input and a clear input, and wherein the interface driver is configured to provide set and clear signals to each of the flip-flops.
8. The circuit of claim 2 , wherein the interface driver is configured to transfer data to the plurality of enabled flip-flops in parallel.
9. The circuit of claim 1 , wherein the circuit comprises an integrated circuit.
10. The circuit of claim 1 , wherein the nonvolatile memory comprises an electrically-erasable read-only (EEPROM) memory.
11. The circuit of claim 1 , wherein the nonvolatile memory comprises one-time programmable (OTP) memory.
12. The circuit of claim 11 , wherein the OTP memory comprises FLASH memory.
13. The circuit of claim 11 , wherein the OTP comprises ROM.
14. The circuit of claim 1 , wherein the plurality of (N) multiplexers corresponds in number to the plurality of (N) flip-flops.
15. The circuit of claim 1 , wherein the plurality of flip-flops comprises N flip-flops and the plurality of multiplexers comprises N-1 multiplexers.
16. The circuit of claim 15 , wherein the plurality of multiplexers is connected to the plurality of flip-flops, and wherein a first flip-flop in the serial configuration is not connected to a multiplexor.
17. The circuit of claim 16 , wherein the first flip-flop is configured to receive data from the serial-in line.
18. The circuit of claim 1 , wherein the plurality of flip-flops comprises set-reset (S-R) flip-flops.
19. The circuit of claim 1 , wherein the plurality of flip-flops comprises JK flip-flops.
20. The circuit of claim 1 , wherein the plurality of flip-flops comprises data (D) flip-flops.
21. The circuit of claim 1 , wherein the plurality of flip-flops comprises toggle (T) flip-flops.
22. The circuit of claim 1 , wherein the output data format comprises a serial format.
23. A configurable variable-length shift register integrated circuit (IC) for adjusting an output data format to a desired bit-length for data communication, the IC comprising:
a plurality of flip-flops connected in a serial configuration, wherein the plurality of flip-flops is connected to a serial-in line and a clock line having, wherein in each flip-flop includes a data input, a clock input configured to receive a clock signal from the clock line, and a data output, and wherein the plurality of flip-flops includes a serial-out line;
a plurality of multiplexers connected to the plurality of flip-flops, wherein each multiplexor includes first and second data inputs and a control input, wherein the control input selects between the data inputs, and wherein each multiplexer includes an output connected to the input of a respective flip-flop;
a nonvolatile memory connected to the plurality of multiplexers and configured to enable one or more flip-flops by configuration of the plurality of multiplexers, wherein the register-length indication corresponds to a selected number of flip-flops selected for enablement;
a programming interface connected to the nonvolatile memory and configured to allow a user to input the register-length indication; and
an interface driver configured to communicate with the plurality of flip-flops and one or more device registers, wherein the interface driver is connected to the output of each flip-flop, and wherein the interface driver is configured to move data between the plurality of flip-flops and the one or more device registers;
wherein the nonvolatile memory is operative to configure the plurality of multiplexers to enable a plurality of enabled flip-flops having a number of enabled flip-flops corresponding to the register-length indication, and
wherein the plurality of enabled flip-flops of the variable-length register is configured to produce a data output with an output data format having a desired bit-length corresponding to the number of enabled flip-flops.
24. The IC of claim 23 , wherein the nonvolatile memory comprises an electrically-erasable read-only (EEPROM) memory.
25. The IC of claim 23 , wherein the nonvolatile memory comprises one-time programmable (OTP) memory.
26. The circuit of claim 25 , wherein the OTP memory comprises FLASH memory.
27. The circuit of claim 25 , wherein the OTP comprises ROM.
28. The IC of claim 23 , wherein the interface driver comprises a serial interface.
29. The circuit of claim 28 , wherein the serial interface comprises a serial-peripheral interface (SPI).
30. The circuit of claim 28 , wherein the serial interface comprises a universal asynchronous receiver/transmitter (UART) interface.
31. The circuit of claim 28 , wherein the serial interface comprises an I2C interface.
32. The IC of claim 28 , wherein the IC is configured for controlling a motor driver.
33. The IC of claim 23 , wherein each of the flips-flops of the plurality of flip-flops includes a set input and a clear input, and wherein the interface driver is configured to provide set and clear signals to each of the flip-flops.
34. The IC of claim 23 , wherein the plurality of (N) multiplexers corresponds in number to the plurality of (N) flip-flops.
35. The IC of claim 23 , wherein the plurality of flip-flops comprises N flip-flops and the plurality of multiplexers comprises N-1 multiplexers.
36. The IC of claim 35 , wherein the plurality of multiplexers is connected to the plurality of flip-flops, wherein a first flip-flop in the serial configuration is not connected to a multiplexor.
37. The IC of claim 36 , wherein the first flip-flop is configured to receive data from the serial-in line.
38. The IC of claim 23 , wherein the plurality of flip-flops comprises set-reset (S-R) flip-flops.
39. The IC of claim 23 , wherein the plurality of flip-flops comprises JK flip-flops.
40. The IC of claim 23 , wherein the plurality of flip-flops comprises data (D) flip-flops.
41. The IC of claim 23 , wherein the plurality of flip-flops comprises toggle (T) flip-flops.
42. The IC of claim 23 , wherein the interface driver is connected to one or more device registers.
43. The IC of claim 42 , wherein the one or more device registers are connected to transducer circuitry.
44. The IC of claim 43 , wherein the transducer circuitry comprises a sensor.
45. The IC of claim 44 , wherein the sensor comprises a magnetic field sensor.
46. The IC of claim 45 , wherein the magnetic field sensor comprises one or more Hall effect elements.
47. The IC of claim 45 , wherein the magnetic field sensor comprises one or more magnetoresistance elements.
48. The IC of claim 44 , wherein the sensor comprises a temperature sensor.
49. The IC of claim 44 , wherein the sensor comprises a current sensor.
50. The IC of claim 43 , wherein the transducer circuitry comprises an analog-to-digital converter (ADC).