Smart prefetching for remote memory

1. A computer system for prefetching pages from a remote memory, the system comprising:

a processor installed in a first CPU socket and executing an application program;

a local memory; and

a field programmable gate array (FPGA) installed in a second CPU socket and connected to the processor via a coherence interconnect, wherein the FPGA is configured to:

detect on the coherence interconnect that a cache-line access made by the processor executing the application program is an access to a cache line containing page table data of the application program;

identify data pages that are referenced by the page table data;

initiate a fetch of a data page, which is one of the identified data pages; and

store the fetched data page in the local memory.

2. The computer system of claim 1 , wherein the FPGA is further configured to:

assign priorities to the identified data pages, wherein a fetch of the identified data pages are to be initiated in the order of the assigned priorities.

3. The computer system of claim 2 , wherein the FPGA is further configured to:

track cache-line accesses to the identified data pages, wherein the priorities to the identified data pages are assigned based on the number of cache-line accesses.

4. The computer system of claim 3 , wherein the identified data pages having a higher number of cache-line accesses relative to the other identified data pages are assigned a higher priority than the other identified data pages.

5. The computer system of claim 1 , wherein the FPGA is further configured to:

track cache-line accesses to the identified data pages that have been fetched and stored in the local memory;

determine that some of the identified data pages are unused based on the cache-line accesses; and

remove the identified data pages that are determined to be unused from the local memory.

6. The computer system of claim 5 , wherein the local memory includes a first local memory of the processor and a second local memory of the FPGA and the identified data pages are removed from the second local memory.

7. The computer system of claim 1 , wherein

the coherence interconnect has a timeout interval, and

the FPGA is further configured to store in the local memory additional data pages that are fetched within the timeout interval of the coherence interconnect.

8. A method of prefetching pages from a remote memory for a processor installed in a first CPU socket, by a field programmable gate array (FPGA) installed in a second CPU socket and connected to the processor via a coherence interconnect, the method comprising:

detecting on the coherence interconnect that a cache-line access made by the processor executing an application program is an access to a cache line containing page table data of the application program;

identifying data pages that are referenced by the page table data;

initiating a fetch of a data page, which is one of the identified data pages; and

storing the fetched data page in a local memory.

9. The method of claim 8 , further comprising:

assigning priorities to the identified data pages, wherein a fetch of the identified data pages are to be initiated in the order of the assigned priorities.

10. The method of claim 9 , further comprising:

tracking cache-line accesses to the identified data pages, wherein the priorities to the identified data pages are assigned based on the number of cache-line accesses.

11. The method of claim 10 , wherein the identified data pages having a higher number of cache-line accesses relative to the other identified data pages are assigned a higher priority than the other identified data pages.

12. The method of claim 8 , further comprising:

tracking cache-line accesses to the identified data pages that have been fetched and stored in the local memory;

determining that some of the identified data pages are unused based on the cache-line accesses; and

removing the identified data pages that are determined to be unused from the local memory.

13. The method of claim 12 , wherein the local memory includes a first local memory of the processor and a second local memory of the FPGA and the identified data pages are removed from the second local memory.

14. The method of claim 8 , wherein

the coherence interconnect has a timeout interval, and

additional data pages that are fetched within the timeout interval of the coherence interconnect are stored in the local memory.

15. A non-transitory computer-readable medium comprising instructions to be executed in a field programmable gate array (FPGA) that is connected to a processor executing an application program, wherein the processor is installed in a first CPU socket and the FPGA is installed in a second CPU socket and connected to the processor via a coherence interconnect, and the instructions, when executed in the FPGA, causes the FPGA to carry out a method of prefetching pages from a remote memory, the method comprising:

detecting on the coherence interconnect that a cache-line access made by the processor executing the application program is an access to a cache line containing page table data of the application program;

identifying data pages that are referenced by the page table data;

initiating a fetch of a data page, which is one of the identified data pages; and

storing the fetched data page in a local memory.

16. The non-transitory computer-readable medium of claim 15 , the method further comprising:

assigning priorities to the identified data pages, wherein a fetch of the identified data pages are to be initiated in the order of the assigned priorities.

17. The non-transitory computer-readable medium of claim 16 , the method further comprising:

tracking cache-line accesses to the identified data pages, wherein the priorities to the identified data pages are assigned based on the number of cache-line accesses.

18. The non-transitory computer-readable medium of claim 17 , wherein the identified data pages having a higher number of cache-line accesses relative to the other identified data pages are assigned a higher priority than the other identified data pages.

19. The non-transitory computer-readable medium of claim 15 , the method further comprising:

tracking cache-line accesses to the identified data pages that have been fetched and stored in the local memory;

determining that some of the identified data pages are unused based on the cache-line accesses; and

removing the identified data pages that are determined to be unused from the local memory.

20. The non-transitory computer-readable medium of claim 15 , wherein

the coherence interconnect has a timeout interval, and

additional data pages that are fetched within the timeout interval of the coherence interconnect are stored in the local memory.