Circuits having enhanced electrical isolation
Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.
1 . A device, comprising:
a circuit cell; and
an isolation structure to electrically isolate the circuit cell, the isolation structure comprising:
a p-type substrate;
a first series of p-type material extending to the p-type substrate;
a second series of p-type material extending to the p-type substrate, wherein the first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material, wherein the first series of p-type material comprises a first p-type well layer, a second p-type well layer and a third p-type well layer, which extends to the p-type substrate;
a doped p-type base layer located between the first p-type well layer and the circuit cell, wherein the base layer contacts the first p-type well layer and the second p-type well layer;
an n well layer between the base layer and the circuit cell;
a p plus layer above the first p-type well layer;
an n buried layer extending from the third p-type well layer of the first series of p-type material to the second series of p-type material; and
a diffusion layer on the n buried layer, wherein the diffusion layer comprises an n epi layer, wherein the n epi layer contacts the base layer, the n well layer, the second p-type well layer, and the third p-type well layer.
2 . The device according to claim 1 , wherein the n epi layer comprises an active layer.
3 . The device according to claim 2 , further including a cell p-type well layer on the n epi layer.
4 . The device according to claim 3 , further including a cell n well layer on the cell p-type well layer.
5 . The device according to claim 4 , wherein the circuit cell includes the cell p-type well layer.
6 . The device according to claim 1 , wherein the circuit cell comprises a memory cell.
7 . The device according to claim 1 , wherein the circuit cell comprises a FLASH memory cell.
8 . The device according to claim 1 , wherein the first series of p-type material comprises a first deep trench isolation structure and the second series of p-type material comprises a second deep trench isolation structure.
9 . The device according to claim 8 , wherein the first deep trench isolation structure comprises a dielectric material.
10 . The device according to claim 9 , wherein the dielectric material comprises an oxide.
11 . The device according to claim 9 , wherein the first deep trench isolation structure includes a conductive material in the dielectric material to provide a conductive path to the p-type substrate.
12 . A method, comprising:
providing a circuit cell; and
providing an isolation structure to electrically isolate the circuit cell, the isolation structure comprising:
a p-type substrate;
a first series of p-type material extending to the p-type substrate; and
a second series of p-type material extending to the p-type substrate, wherein the first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material, wherein the first series of p-type material comprises a first p-type well layer, a second p-type well layer and a third p-type well layer, which extends to the p-type substrate;
a doped p-type base layer located between the first p-type well layer and the circuit cell, wherein the base layer contacts the first-p-type first p-type well layer and the second p-type well layer;
an n well layer between the base layer and the circuit cell;
a p plus layer above the first p-type well layer;
an n buried layer extending from the third p-type well layer of the first series of p-type material to the second series of p-type material; and
a diffusion layer on the n buried layer, wherein the diffusion layer comprises an n epi layer, wherein the n-epi n epi layer contacts the base layer, the n well layer, the second p-type well layer, and the third p-type well layer.
13 . The method according to claim 12 , wherein the n epi layer comprises an active layer.
14 . The method according to claim 13 , further including employing a cell p-type well layer on the n epi layer.
15 . The method according to claim 14 , further including employing a cell n well layer on the cell p-type well layer.
16 . The method according to claim 15 , wherein the circuit cell includes the cell p-type well layer.
17 . The method according to claim 12 , wherein the circuit cell comprises a memory cell.
18 . The method according to claim 12 , wherein the circuit cell comprises a FLASH memory cell.
19 . The method according to claim 12 , wherein the first series of p-type material comprises a first deep trench isolation structure and the second series of p-type material comprises a second deep trench isolation structure.
20 . The method according to claim 19 , wherein the first deep trench isolation structure comprises a dielectric material.
21 . The method according to claim 20 , wherein the dielectric material comprises an oxide.
22 . The method according to claim 20 , wherein the first deep trench isolation structure includes a conductive material in the dielectric material to provide a conductive path to the p-type substrate.