ELECTROSTATIC DISCHARGE PROTECTION DEVICE INCLUDING PARASITIC MOSFET FORMED USING TRENCH

1 . A semiconductor device comprising:

a first region;

a second region; and

a trench separating the first region from the second region, the trench comprising a trench liner comprising a dielectric, and a semiconductor material surrounded by the trench liner;

wherein the first region comprises:

a first buried layer implanted in a substrate;

a first stack of layers comprising:

a first middle layer located above the first buried layer;

a first well located on and in contact with the first middle layer; and

a second well in contact with the first well,

wherein the second region comprises a second stack of layers,

wherein the trench is in contact with the second well and extends into the substrate below the first buried layer,

wherein in response to a voltage difference between the first region and the second region exceeding a threshold voltage, a conduction current is formed,

wherein a distance of the first stack of layers to the trench controls the conduction current to activate a transistor to function as a voltage clamp,

wherein a source of the transistor is formed by the first stack of layers, a gate of the transistor is formed by the second stack of layers and a drain of the transistor is formed in the substrate,

wherein the gate of the transistor and the drain of the transistor are electrically tied to each other, and

wherein a gate dielectric of the transistor is formed by the trench liner.

2 . The semiconductor device of claim 1 , further comprising an epitaxial layer in contact with the first buried layer, the first middle layer, the first well, the second well, and the trench.

3 . The semiconductor device of claim 2 , wherein the first stack of layers further comprises a second buried layer in contact with the first buried layer, the first middle layer and the epitaxial layer.

4 . The semiconductor device of claim 3 , wherein the first buried layer and the second well have a first-type dopant, and

wherein the substrate, the first middle layer, the first well, and the second buried layer have a second-type dopant,

wherein the first-type dopant is one of a n-type dopant or a p-type dopant, and

wherein the second-type dopant is the other one of the n-type dopant or the p-type dopant.

5 . The semiconductor device of claim 4 , wherein the first buried layer and the second well have a first-type dopant, and

wherein the substrate, the first middle layer, and the first well,

wherein the first-type dopant is one of a n-type dopant or a p-type dopant, and

wherein the second-type dopant is the other one of the n-type dopant or the p-type dopant.

6 . The semiconductor device of claim 1 , wherein the first stack of layers is separated from the trench by less than 8 microns.

7 . The semiconductor device of claim 1 , wherein the first stack of layers is separated from the trench by about 4 microns.

8 . The semiconductor device of claim 1 , wherein the threshold voltage is greater than 90 volts.

9 . The semiconductor device of claim 1 , wherein the threshold voltage is greater than 100 volts.

10 . The semiconductor device of claim 1 , wherein the semiconductor material is silicon.

11 . The semiconductor device of claim 10 , wherein the silicon is polycrystalline silicon.

12 . The semiconductor device of claim 1 , wherein the second stack of layers comprises:

a third buried layer implanted in the substrate;

a second middle layer directly on and in contact with the third buried layer; and

a third well directly on and in contact with the second middle layer.

13 . The semiconductor device of claim 12 , wherein the third buried layer, the second middle layer and the third well are in direct contact with the trench.

14 . The semiconductor device of claim 1 , wherein the transistor is a p-type metal-oxide-semiconductor field-effect transistor (MOSFET).

15 . The semiconductor device of claim 1 , wherein the transistor is a n-type metal-oxide-semiconductor field-effect transistor (MOSFET).