Oscillator monitoring circuits for different oscillator domains
Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.
1. A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:
means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 16 MHZ, wherein the means for synchronization is disposed in a domain of the second oscillator.
2. The clock monitor of claim 1 , wherein the comparison circuitry comprises a comparator configured to compare the count value to upper and/or lower threshold values and to determine whether the count value indicates a frequency error.
3. The clock monitor circuit of claim 2 , wherein the comparison circuitry is configured to detect the clock signal from the first oscillator being stuck.
4. The clock monitor circuit of claim 2 , wherein the comparison circuitry is configured to detect the frequency difference between the two clock signals being outside of a predetermined range.
5. The clock monitor of claim 1 , further comprising an edge detector configured to detect transitions between one digital signal state and another state of the synchronized clock signal.
6. The clock monitor of claim 5 , wherein the edge detector comprises a rising-edge detector.
7. A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:
means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 2 MHz, wherein the means for synchronization is disposed in a domain of the second oscillator.
8. A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:
means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the means for synchronization is disposed in a domain of the second oscillator.
9. The clock monitor of claim 8 , wherein the comparison circuitry comprises a finite state machine (FSM).
10. A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:
means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 250 kHz, wherein the means for synchronization is disposed in the domain of the second oscillator.
11. The clock monitor of claim 10 , wherein the means for synchronization comprises a plurality of flip-flops configured in series.
12. The clock monitor of claim 10 , wherein the means for synchronization comprises a MUX synchronizer.
13. The clock monitor of claim 10 , wherein the means for synchronization comprises a toggle synchronizer.
14. The clock monitor of claim 10 , wherein the means for synchronization comprises a dual-clock FIFO synchronizer.
15. The clock monitor of claim 10 , wherein the plurality of oscillators is disposed in an integrated circuit.
16. The clock monitor of claim 10 , wherein the comparison circuitry is configured to implement a predetermined range including upper and lower thresholds.
17. The clock monitor of claim 16 , wherein the upper and lower thresholds each comprise a pair of different thresholds.
18. A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:
a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.
19. The clock monitor circuit of claim 18 , wherein the comparison means comprises a comparator configured to compare the count value to upper and/or lower threshold values, to determine whether the count value indicates a frequency error.
20. The clock monitor circuit of claim 18 , wherein the comparison circuitry is configured to detect the clock signal from the first oscillator being stuck.
21. The clock monitor circuit of claim 18 , wherein the comparison circuitry is configured to detect the frequency difference between the two clock signals being outside of a predetermined range.
22. The clock monitor circuit of claim 18 , further comprising an edge detector configured to detect transitions between one digital signal state and another state of the synchronized clock signal.
23. The clock monitor circuit of claim 22 , wherein the edge detector comprises a rising-edge detector.
24. A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:
a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 2 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.
25. A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:
a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.
26. The clock monitor circuit of claim 25 , wherein the comparison means comprises a finite state machine (FSM).
27. A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:
a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
a counter configured to produce a count value based on synchronized clock signal; and
comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 250 kHz, wherein the synchronizer is disposed in the domain of the second oscillator.
28. The clock monitor circuit of claim 27 , wherein the synchronizer comprises a plurality of flip-flops configured in series.
29. The clock monitor circuit of claim 27 , wherein the synchronizer comprises a MUX synchronizer.
30. The clock monitor circuit of claim 27 , wherein the synchronizer comprises a toggle synchronizer.
31. The clock monitor circuit of claim 27 , wherein the synchronizer comprises a dual-clock FIFO synchronizer.
32. The clock monitor circuit of claim 27 , wherein the comparison means is configured to implement a predetermined range including upper and lower thresholds.
33. The clock monitor circuit of claim 32 , wherein the upper and lower thresholds each comprise a pair of different thresholds.
34. The clock monitor circuit of claim 27 , wherein the clock monitor circuit comprises a microcontroller.