Reliable non-volatile memory download approach
According to an embodiment, a method includes adjusting a reference generator into a first configuration based on a temporary trim value resulting, in a first reference voltage and a first reference current being generated for a first memory. The method further includes performing an integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current. The initial set of data includes a first trim value. The method further includes downloading contents from the first memory into a second memory in response to a successful integrity check after adjusting the reference generator into a second configuration. In the second configuration, the reference generator generates a second reference voltage and a second reference current for the first memory. The reference generator is adjusted by the first trim value in response to a successful integrity check.
1. A method, comprising:
adjusting, by a controller, a reference generator into a first configuration, wherein, in the first configuration, the reference generator is configured to generate a first reference voltage and a first reference current for a first memory, the reference generator adjusted by a temporary trim value in the first configuration;
performing, by the controller, a download integrity check on an initial set of data downloaded from the first memory based on the first reference voltage and the first reference current, the initial set of data comprising a first trim value; and
downloading, by the controller, contents from the first memory into a second memory in response to a successful download integrity check after adjusting the reference generator into a second configuration, wherein, in the second configuration, the reference generator is configured to generate a second reference voltage and a second reference current for the first memory, the reference generator adjusted by the first trim value in response to a successful download integrity check.
2. The method of claim 1 , further comprising initializing the second memory to a default configuration in response to receiving a power on reset signal.
3. The method of claim 1 , wherein the temporary trim value is a pre-defined trim value from a set of pre-defined trim values accessible to the controller.
4. The method of claim 1 , further comprising transitioning a finite state machine (FSM) circuit of the controller from one state to a next in response to an unsuccessful download integrity check, wherein, in each state, the FSM circuit adjusts the reference generator based on a different temporary trim value.
5. The method of claim 1 , wherein the first memory is a non-volatile memory, and wherein the second memory is a volatile memory.
6. The method of claim 1 , wherein the initial set of data comprises a passkey, the first trim value, an inverted first trim value, or a combination thereof, wherein a successful download integrity check comprises verifying, by the controller, that the passkey matches a pre-determined value, that the inverted first trim value is an inverted value of the first trim value, or a combination thereof.
7. The method of claim 1 , further comprising:
storing the first trim value in the second memory after determining a successful download integrity check; and
adjusting the reference generator into the second configuration based on the first trim value stored in the second memory.
8. A circuit, comprising:
a reference generator configured to generate a reference voltage and a reference current, wherein the reference voltage, the reference current, or both are adjustable based on a trim value;
a first memory configured to store a first trim value for the reference generator in an initial set of data;
a second memory; and
a controller configured to:
determine a temporary trim value to be forwarded to the reference generator;
perform a download integrity check on the initial set of data downloaded from the first memory based on a first reference voltage and a first reference current provided by the reference generator after being adjusted based on the temporary trim value; and
download a second set of data from the first memory to the second memory based on a second reference voltage and a second reference current provided by the reference generator after being adjusted based on the first trim value in response to a successful download integrity check.
9. The circuit of claim 8 , where the second memory is initialized to a default configuration in response to receiving a power on reset signal.
10. The circuit of claim 8 , wherein the temporary trim value is a pre-defined trim value from a set of pre-defined trim values accessible to the controller.
11. The circuit of claim 8 , wherein the controller comprises a finite state machine (FSM) circuit, the FSM circuit configured to transition from one state to a next in response to an unsuccessful download integrity check, wherein, in each state, the FSM circuit adjusts the reference generator based on a different temporary trim value.
12. The circuit of claim 8 , wherein the first memory is a non-volatile memory, and wherein the second memory is a volatile memory.
13. The circuit of claim 8 , wherein the initial set of data comprises a passkey, the first trim value, an inverted first trim value, or a combination thereof, wherein a successful download integrity check comprises verifying, by the controller, that the passkey matches a pre-determined value, that the inverted first trim value is an inverted value of the first trim value, or a combination thereof.
14. The circuit of claim 8 , wherein the controller is further configured to download the first trim value to the second memory after determining a successful download integrity check, and wherein the reference generator is adjusted based on the first trim value stored in the second memory.
15. A device, comprising:
a processor; and
a circuit, comprising:
a reference generator configured to generate a reference voltage and a reference current, wherein the reference voltage, the reference current, or both are adjustable based on a trim value;
a first memory configured to store a first trim value for the reference generator in an initial set of data;
a second memory accessible by the processor; and
a controller configured to:
determine a temporary trim value to be forwarded to the reference generator;
perform a download integrity check on the initial set of data downloaded from the first memory based on a first reference voltage and a first reference current provided by the reference generator after being adjusted based on the temporary trim value; and
download a second set of data from the first memory to the second memory based on a second reference voltage and a second reference current provided by the reference generator after being adjusted based on the first trim value in response to a successful download integrity check.
16. The device of claim 15 , where the second memory is initialized to a default configuration in response to receiving a power on reset signal.
17. The device of claim 15 , wherein the temporary trim value is a pre-defined trim value from a set of pre-defined trim values accessible to the controller.
18. The device of claim 15 , wherein the controller comprises a finite state machine (FSM) circuit, the FSM circuit configured to transition from one state to a next in response to an unsuccessful download integrity check, wherein, in each state, the FSM circuit adjusts the reference generator based on a different temporary trim value.
19. The device of claim 15 , wherein the first memory is a non-volatile memory, and wherein the second memory is a volatile memory.
20. The device of claim 15 , wherein the initial set of data comprises a passkey, the first trim value, an inverted first trim value, or a combination thereof, wherein a successful download integrity check comprises verifying, by the controller, that the passkey matches a pre-determined value, that the inverted first trim value is an inverted value of the first trim value, or a combination thereof.