PLL with a controlled range of output frequency for MEMS gyroscope
According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.
1 . A phased-locked loop (PLL) circuit for generating demodulation signals in a gyroscope system, the PLL circuit comprising:
a phase frequency detector coupled to an output of a gyroscope in the gyroscope system, the phase frequency detector configured to generate an error signal by comparing an input reference signal with a feedback comparison frequency signal;
a charge pump configured to translate error information of the error signal into a first analog control signal;
a programmable clamp circuit configured to generate a second analog control signal from the first analog control signal, the programmable clamp circuit being a current mirror controller oscillator with programmable transistors;
a voltage-controlled oscillator configured to receive the second analog control signal and generate an output signal having a regulated frequency, wherein the regulated frequency is set by the second analog control signal generated by the programmable clamp circuit, and wherein the programmable transistors are set during a calibration phase based on a maximum value of the regulated frequency; and
a frequency divider configured to provide the feedback comparison frequency signal to the phase frequency detector based on the regulated frequency of the output signal.
2 . The PLL circuit of claim 1 , wherein the programmable transistors are set by retrieving settings for each programmable transistor from a memory.
3 . The PLL circuit of claim 2 , wherein the settings for each programmable transistor are stored in the memory during the calibration phase, and wherein the settings are retrieved from the memory during a startup phase of the gyroscope system.
4 . The PLL circuit of claim 1 , wherein the calibration phase comprises sweeping settings for each programmable transistor to minimize an error signal between the output signal of the PLL circuit and a target value corresponding to the maximum value of the regulated frequency.
5 . The PLL circuit of claim 4 , wherein the PLL circuit is configured in an open loop configuration during the calibration phase, and wherein the first analog control signal is set to zero volts for a p-channel current mirror controlled oscillator or set to a supply voltage of the gyroscope system for an n-channel current mirror controlled oscillator.
6 . The PLL circuit of claim 1 , wherein the calibration phase comprises sweeping settings for each programmable transistor to minimize an error signal between the output signal of the PLL circuit and a target value corresponding to the maximum value of the regulated frequency minus a margin.
7 . The PLL circuit of claim 1 , wherein the programmable transistors comprise n-channel transistors and p-channel transistors arranged as current mirrors.
8 . The PLL circuit of claim 7 , wherein a programmable transistor is configured as a collection of transistors arranged in parallel, and wherein a subset or entirety of the transistors in the collection is selectively enabled or disabled to set an effective width-to-length ratio.
9 . A system, comprising:
a gyroscope configured to detect changes in a vibration of a proof mass due to a drive motion by generating first signals;
a charge-to-voltage converter configured to convert the first signals to a differential sine wave signal, the first signals being charge signals, and the differential sine wave signal being equivalent voltage signals to the first signals; and
a drive comparator configured to eliminate false pulses due to high-frequency signals and noise superimposed on top of the differential sine wave signal;
a phase frequency detector coupled to an output of the drive comparator, the phase frequency detector configured to generate an error signal by comparing a first output signal at the output of the drive comparator with a feedback comparison frequency signal;
a charge pump configured to translate error information of the error signal into a first analog control signal;
a programmable clamp circuit configured to generate a second analog control signal from the first analog control signal, the programmable clamp circuit being a current mirror controller oscillator with programmable transistors;
a voltage-controlled oscillator configured to receive the second analog control signal and generate a second output signal having a regulated frequency, wherein the regulated frequency is set by the second analog control signal generated by the programmable clamp circuit, and wherein the programmable transistors are set during a calibration phase based on a maximum value of the regulated frequency; and
a frequency divider configured to provide the feedback comparison frequency signal to the phase frequency detector based on the regulated frequency of the second output signal.
10 . The system of claim 9 , wherein the programmable transistors are set by retrieving settings for each programmable transistor from a memory.
11 . The system of claim 10 , wherein the settings for each programmable transistor are stored in the memory during the calibration phase, and wherein the settings are retrieved from the memory during a startup phase of the system.
12 . The system of claim 9 , wherein the calibration phase comprises sweeping settings for each programmable transistor to minimize an error signal between the second output signal and a target value corresponding to the maximum value of the regulated frequency.
13 . The system of claim 12 , wherein the PLL circuit is configured in an open loop configuration during the calibration phase, and wherein the first analog control signal is set to zero volts for a p-channel current mirror controlled oscillator or set to a supply voltage of the system for an n-channel current mirror controlled oscillator.
14 . The system of claim 12 , wherein the calibration phase comprises sweeping settings for each programmable transistor to minimize an error signal between the second output signal and a target value corresponding to the maximum value of the regulated frequency minus a margin.
15 . A method for calibrating a phased-locked loop (PLL) circuit used to generate modulation signals in a gyroscope system, the method comprising:
arranging the PLL circuit in an open loop configuration;
setting an input voltage to a programmable clamp circuit of the PLL circuit to zero volts in response to the programmable clamp circuit being configured as a p-channel current mirror controlled oscillator or set to a supply voltage of the gyroscope system in response to the programmable clamp circuit being configured as an n-channel current mirror controlled oscillator;
sweeping the settings for each programmable transistor of the programmable clamp circuit to minimize an error signal between an output signal of the PLL circuit and a target value corresponding to a maximum value of a regulated frequency at an output of the PLL circuit;
storing in a memory the settings for each programmable transistor based on determining values for each programmable transistor with a minimal error signal during the sweep; and
applying the settings for each programmable transistor from memory during a startup phase of the gyroscope system.
16 . The method of claim 15 , further comprising sweeping settings for each programmable transistor to minimize an error signal between the output signal of the PLL circuit and a target value corresponding to a maximum value of the regulated frequency minus a margin.
17 . The method of claim 15 , wherein the target value corresponds to a maximum frequency of the output signal of the PLL circuit that is within an operating range of a digital circuit coupled to an output of the PLL circuit.
18 . The method of claim 15 , wherein the target value corresponds to a maximum frequency of the output signal of the PLL circuit that is within an operating range of a digital circuit with a margin, the digital circuit coupled to an output of the PLL circuit.
19 . The method of claim 15 , further comprising generating, by a controller coupled to the programmable clamp circuit, settings for each programmable transistor during the sweep.
20 . The method of claim 15 , further comprising generating a control signal at the output of the programmable clamp circuit as an input to a voltage-controlled oscillator of the PLL circuit, wherein the voltage-controlled oscillator generates the output signal of the PLL circuit.