ASYNCHRONOUS ASIC

1 . An electronic device comprising:

circuitry configured to:

receive a first clock, the first clock configured to operate at a frequency; and

receive a second clock and a third clock, wherein:

the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,

the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and

each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;

wherein:

each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;

the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and

the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.

2 . The electronic device of claim 1 , wherein each clock candidate of the plurality of clock candidates is configured to operate at the frequency of the first clock.

3 . The electronic device of claim 1 , wherein the second clock is associated with a phase shift of 180 degrees.

4 . The electronic device of claim 1 , wherein the circuitry is further configured to synchronize with the first clock.

5 . The electronic device of claim 1 , wherein one or more of the respective clock candidates is selected to reduce a noise of the electronic device.

6 . The electronic device of claim 5 , wherein the noise is associated with transistor resonance.

7 . The electronic device of claim 1 , further comprising a memory, wherein:

the electronic device is configured to perform a data write operation with respect to the memory, the data write operation synchronized with the first clock, and

the electronic device is further configured to perform a data read operation with respect to the memory, the data read operation synchronized with the second clock.

8 . The electronic device of claim 1 , further comprising a data bus electronically coupled to the first circuitry and electronically coupled to a second circuitry of the electronic device, wherein the first circuitry is further configured to transmit data to the second circuitry via the data bus, and wherein the second circuitry is configured to synchronize with the second clock.

9 . The electronic device of claim 1 , wherein:

the electronic device comprises one or more latches; and

each latch of the one or more latches is configured to:

receive data from the circuitry, and

synchronize with a respective clock selected from the plurality of clock candidates based on a latency between the latch and the circuitry.

10 . The electronic device of claim 1 , wherein:

the first clock is associated with a first portion of the circuitry,

the second clock is associated with a second portion of the circuitry,

the third clock is associated with a third portion of the circuitry,

the first portion of the circuitry is distinct from the second portion of the circuitry and is further distinct from the third portion of the circuitry, and

the second portion of the circuitry is distinct from the third portion of the circuitry.

11 . A method, comprising:

receiving, at an electronic device, a first clock, the first clock operating at a frequency; and

receiving, at the electronic device, a second clock and a third clock, wherein:

the second clock operates at the frequency of the first clock and operates with a first phase shift with respect to the first clock,

the third clock operates at the frequency of the first clock and operates with a second phase shift with respect to the first clock, and

each of the second clock and third clock is associated with a respective clock candidate selected from a plurality of clock candidates;

wherein:

each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;

the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and

the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.

12 . The method of claim 11 , wherein the each clock candidate of the plurality of clock candidates is operating at the frequency of the first clock.

13 . The method of claim 11 , wherein the second clock is associated with a phase shift of 180 degrees.

14 . The method of claim 11 , further comprising synchronizing circuitry of the electronic device with the first clock.

15 . The method of claim 11 , wherein one or more of the respective clock candidates is selected to reduce a noise of the electronic device.

16 . The method of claim 15 , wherein the noise is associated with transistor resonance.

17 . The method of claim 11 , further comprising:

performing a data write operation with respect to a memory of the electronic device, the data write operation synchronized with the first clock, and

performing a data read operation with respect to the memory, the data read operation synchronized with the second clock.

18 . The method of claim 11 , further comprising:

receiving data via a latch; and

synchronizing with a respective clock selected from the plurality of clock candidates based on a latency between the latch and a circuitry of the electronic device.

19 . The method of claim 11 , wherein:

the first clock is associated with a first portion of the circuitry,

the second clock is associated with a second portion of the circuitry,

the third clock is associated with a third portion of the circuitry,

the first portion of the circuitry is distinct from the second portion of the circuitry and is further distinct from the third portion of the circuitry, and

the second portion of the circuitry is distinct from the third portion of the circuitry.

20 . A non-transitory computer-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform a method comprising:

receiving, at an electronic device, a first clock, the first clock operating at a frequency; and

receiving, at the electronic device, a second clock and a third clock, wherein:

the second clock operates at the frequency of the first clock and operates with a first phase shift with respect to the first clock,

the third clock operates at the frequency of the first clock and operates with a second phase shift with respect to the first clock, and

each of the second clock and the third clock is associated with a respective clock candidate selected from a plurality of clock candidates;

wherein:

each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;

the selecting the respective clock candidate associated with the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and

the selecting the respective clock candidate associated with the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.