IP Library Granted Patent US 12,555,605
Granted Patent B2
US 12,555,605 · App. 18/797,467 · Granted Feb 17, 2026

Dual channel burst gain switching in a data storage device

Inventors: Guoxiao Guo (Irvine, CA); Gary Herbst (San Jose, CA); Byung Kim (Gilroy, CA); Tianyu Jiang (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G11B19/045G11B5/027G11B5/59688
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Quick Facts
Patent No.
US 12,555,605
App. No.
18/797,467
Granted
Feb 17, 2026
Kind
B2
Abstract

Example control circuitry, data storage devices, and methods to use dual servo channels for burst gain switching are described. The data storage device may include two servo channels, such as the dual channels in a two-dimensional magnetic recording channel, that receive read signals for the same servo sector in parallel. One channel is calibrated to use a gain value for a first portion of the servo pattern, such as the preamble and Gray code for the servo address mark, and the other channel is calibrated to use a different gain value for a second portion of the servo pattern, such as the burst pattern. The resulting signal values may then be combined to determine the position error signal. Both channels may be configured to use different gain values for different portions of the read signal with corresponding gain switching and combining them may use the most reliable portions of each signal.

Claims (81)

1 . A data storage device, comprising:

a first servo channel circuit configured to:

receive a first read signal for a servo pattern from a servo sector; and

determine, using a first gain value configured for reading a first portion of the servo pattern, signal values for the first portion of the servo pattern;

a second servo channel circuit configured to:

receive a second read signal for the servo pattern from the servo sector; and

determine, using a second gain value configured for reading a second portion of the servo pattern, signal values for the second portion of the servo pattern, wherein the first gain value and the second gain value are different; and

a servo processor circuit configured to combine the signal values for the first portion and the signal values for the second portion to determine a position error signal of a head.

2 . The data storage device of claim 1 , further comprising:

a storage medium comprising a plurality of servo sectors defining a plurality of servo tracks, wherein the servo sector is from the plurality of servo sectors; and

the head actuated over the storage medium for reading the plurality of servo tracks, wherein:

the head comprises a read element;

the read element is configured to generate an analog read signal; and

the first read signal and the second read signal are based on the analog read signal.

3 . The data storage device of claim 2 , further comprising:

at least one switch between the read element and at least one channel circuit, wherein the at least one switch is configured to provide the analog read signal to the first servo channel circuit and to the second servo channel circuit in parallel with impedance matching.

4 . The data storage device of claim 3 , wherein:

the head comprises a plurality of read elements; and

the servo processor circuit is further configured to select the read element from the plurality of read elements in the head.

5 . The data storage device of claim 1 , further comprising:

a storage medium comprising a plurality of servo sectors defining a plurality of servo tracks, wherein the servo sector is from the plurality of servo sectors; and

the head actuated over the storage medium for reading the plurality of servo tracks, wherein the head comprises:

a first read element configured to:

generate a first analog read signal; and

provide the first analog read signal to the first servo channel circuit for the first read signal; and

a second read element configured to:

generate a second analog read signal; and

provide the second analog read signal to the second servo channel circuit for the second read signal.

6 . The data storage device of claim 5 , wherein:

the servo processor circuit is further configured to use a cross-track separation value to combine the signal values from the first portion and the second portion; and

the cross-track separation value is calibrated for relative positions of the first read element and the second read element.

7 . The data storage device of claim 1 , wherein:

the first portion comprises Gray code values corresponding to a servo address mark; and

the first gain value is calibrated to optimize Gray code detection.

8 . The data storage device of claim 1 , wherein:

the second portion comprises signal values for at least one fine positioning burst; and

the second gain value is calibrated to prevent saturation of the second servo channel circuit.

9 . The data storage device of claim 1 , wherein:

the second servo channel circuit is further configured to:

determine, using a third gain value, signal values for a first portion of the servo sector from the second read signal; and

switch from the third gain value to the second gain value responsive to a gain switch position in the second read signal; and

the gain switch position is calibrated to prevent a settle time for switching to the second gain value from affecting the signal values for the second portion of the servo sector from the second read signal.

10 . A data storage device of claim 1 , wherein the servo processor circuit is further configured to:

determine, based on an amplitude difference ratio for an operating condition, a trigger condition for using the first servo channel circuit and the second servo channel circuit in parallel for servo gain control; and

selectively enable, responsive to the trigger condition being met, the first servo channel circuit and the second servo channel circuit in parallel for servo gain control.

11 . A method comprising:

receiving, by a first servo channel circuit, a first read signal for a servo pattern from a servo sector;

determining, by the first servo channel circuit and using a first gain value configured for reading a first portion of the servo pattern, signal values for the first portion of the servo pattern;

receiving, by a second servo channel circuit, a second read signal for the servo pattern from the servo sector;

determining, by the second servo channel circuit and using a second gain value configured for reading a second portion of the servo pattern, signal values for the second portion of the servo pattern, wherein the first gain value and the second gain value are different; and

combining the signal values for the first portion and the signal values for the second portion to determine a position error signal of a head.

12 . The method of claim 11 , further comprising:

generating, by a read element in the head, an analog read signal, wherein the first read signal and the second read signal are based on the analog read signal.

13 . The method of claim 12 , further comprising:

sending the analog read signal to the first servo channel circuit and the second servo channel circuit in parallel with impedance matching.

14 . The method of claim 13 , further comprising:

selecting, from a plurality of read elements in the head, the read element to send the analog read signal to the first servo channel circuit and the second servo channel circuit.

15 . The method of claim 11 , further comprising:

generating, by a first read element in the head, a first analog read signal;

providing the first analog read signal to the first servo channel circuit for the first read signal;

generating, by a second read element in the head, a second analog read signal; and

providing the second analog read signal to the second servo channel circuit for the second read signal.

16 . The method of claim 15 , further comprising:

using a cross-track separation value to combine the signal values from the first portion and the second portion, wherein the cross-track separation value is calibrated for relative positions of the first read element and the second read element.

17 . The method of claim 11 , wherein:

the first portion comprises Gray code values corresponding to a servo address mark; and

the first gain value is calibrated to optimize Gray code detection.

18 . The method of claim 11 , wherein:

the second portion comprises signal values for at least one fine positioning burst; and

the second gain value is calibrated to prevent saturation of the second servo channel circuit.

19 . The method of claim 11 , further comprising:

determining, by the second servo channel circuit and using a third gain value, signal values for a first portion of the servo sector from the second read signal; and

switching, by the second servo channel circuit, from the third gain value to the second gain value responsive to a gain switch position in the second read signal, wherein the gain switch position is calibrated to prevent a settle time for switching to the second gain value from affecting the signal values for the second portion of the servo sector from the second read signal.

20 . A data storage device comprising:

a first servo channel circuit comprising:

means for receiving a first read signal for a servo pattern from a servo sector; and

means for determining, using a first gain value configured for reading a first portion of the servo pattern, signal values for the first portion of the servo pattern;

a second servo channel circuit comprising:

means for receiving a second read signal for the servo pattern from the servo sector; and

means for determining, using a second gain value configured for reading a second portion of the servo pattern, signal values for the second portion of the servo pattern, wherein the first gain value and the second gain value are different; and

means for combining the signal values for the first portion and the signal values for the second portion to determine a position error signal of a head.

Assignments (2)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2024
From: GUO, GUOXIAO; HERBST, GARY; KIM, BYUNG; JIANG, TIANYU
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 068220/0848 →
Continuity (1)
Related Publication 20260045276A1 · Feb 12, 2026
References Cited (14)
US 6157510A · Schreck · 2000 [cited by examiner]
US 7710676B1 · Chue · 2010 [cited by applicant]
US 7898762B1 · Guo · 2011 [cited by applicant]
US 8693123B1 · Guo · 2014 [cited by applicant]
US 8824081B1 · Guo · 2014 [cited by applicant]
US 8917469B1 · Guo · 2014 [cited by applicant]
US 8970982B1 · Zhou · 2015 [cited by applicant]
US 9013824B1 · Guo · 2015 [cited by applicant]
US 9286926B1 · Dhanda et al. · 2016 [cited by applicant]
US 9704522B2 · Yuan · 2017 [cited by applicant]
US 10109301B1 · French, Jr. · 2018 [cited by applicant]
US 10332557B1 · Mendonsa · 2019 [cited by applicant]
US 20170186454A1 · Asakura · 2017 [cited by applicant]
Xiong et al., Position Error Signal Generation in Hard Disk Drives Based on a Field Programmable Gate Array (FPGA), Microsyst Technol, vol. 19, pp. 1307-1311, (2013). [cited by applicant]