PACKAGE INCLUDING MULTIPLE SEMICONDUCTOR DEVICES
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
1 . (canceled)
2 . (canceled)
3 . An apparatus, comprising:
a common gate conductor having:
a first portion, and
a second portion;
a first semiconductor die and a second semiconductor die coupled to the first portion of the common gate conductor; and
a third semiconductor die coupled to the second portion of the common gate conductor.
4 . The apparatus of claim 3 , wherein the first portion of the common gate conductor is aligned with the second portion.
5 . The apparatus of claim 3 , wherein the common gate conductor has a third portion orthogonal to the second portion.
6 . The apparatus of claim 3 , comprising:
a fourth semiconductor die coupled to the second portion of the common gate conductor.
7 . The apparatus of claim 3 , wherein the first semiconductor die and the second semiconductor die are on opposite sides of the first portion of the common gate conductor.
8 . The apparatus of claim 3 , wherein the common gate conductor defines a first conductive path to the first semiconductor die,
the common gate conductor defines a second conductive path to the second semiconductor die, and
the first conductive path having a length substantially equal to a length of the second conductive path.
9 . The apparatus of claim 8 , wherein the first semiconductor die has a die gate conductor oriented with respect to the common gate conductor so that a length of the first conductive path is minimized.
10 . The apparatus of claim 3 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane, the first semiconductor die has an edge parallel to an edge of the second semiconductor die.
11 . The apparatus of claim 3 , wherein at least one of the first semiconductor die or the second semiconductor die is a silicon carbide die.
12 . The apparatus of claim 3 , wherein the common gate conductor, the first semiconductor die, and the second semiconductor die are included in an inner package,
the apparatus, further comprising:
an outer package including a substrate.
13 . An apparatus, comprising:
a common gate conductor having:
a first portion, and
a second portion;
a first semiconductor die and a second semiconductor die coupled to opposite sides of the first portion of the common gate conductor; and
a third semiconductor die coupled to the second portion of the common gate conductor.
14 . The apparatus of claim 13 , wherein the first portion of the common gate conductor is aligned with the second portion.
15 . The apparatus of claim 14 , wherein the common gate conductor has a third portion orthogonal to the second portion.
16 . The apparatus of claim 13 , comprising:
a fourth semiconductor die on an opposite side of the second portion relative to the third semiconductor die.
17 . The apparatus of claim 13 , wherein the common gate conductor defines a first conductive path to the first semiconductor die,
the common gate conductor defines a second conductive path to the second semiconductor die, and
the first conductive path having a length substantially equal to a length of the second conductive path.
18 . The apparatus of claim 17 , wherein the first semiconductor die has a die gate conductor oriented with respect to the common gate conductor so that a length of the first conductive path is minimized.
19 . The apparatus of claim 13 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane, the first semiconductor die has an edge parallel to an edge of the second semiconductor die.
20 . An apparatus, comprising:
a common gate conductor having:
a first portion,
a second portion, and
a third portion orthogonal to the first portion and the second portion; and
a first semiconductor die and a second semiconductor die coupled to opposite portions of the first portion of the common gate conductor.
21 . The apparatus of claim 20 , further comprising:
a third semiconductor die coupled to the second portion of the common gate conductor.
22 . The apparatus of claim 20 , wherein the first semiconductor die and the second semiconductor die are aligned along a same plane, the first semiconductor die has an edge parallel to an edge of the second semiconductor die.
23 . The apparatus of claim 20 , wherein the common gate conductor defines a first conductive path to the first semiconductor die,
the common gate conductor defines a second conductive path to the second semiconductor die, and
the first conductive path having a length substantially equal to a length of the second conductive path.
24 . The apparatus of claim 23 , wherein the first semiconductor die has a die gate conductor oriented with respect to the common gate conductor so that a length of the first conductive path is minimized.