MDIP SEMICONDUCTOR DEVICE INCLUDING BACKFILLED VIAS
A mirrored die pair (mDiP) semiconductor device includes deep trench vias having portions at the upper and/or lower surfaces of the mDiP device that are backfilled with conductive material. Backfilling the deep trench vias ensures electrically coupled, solid, low resistive bonding, for example between a stack of mDiP semiconductor devices.
1 . A semiconductor device, comprising:
a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising:
a memory die,
a first major planar surface,
a second major planar surface,
a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface; and
conductive backfill material backfilling the concave meniscus in said each via, the backfill material bringing each said via flush with the first major planar surface.
2 . The semiconductor device of claim 1 , wherein the portion of each of the vias comprising the conductive backfill material have enlarged diameters relative to the rest of each of said vias.
3 . The semiconductor device of claim 1 , wherein the portion of each of the vias comprising the conductive backfill material have a trapezoid shape narrowing toward the first major planar surface.
4 . The semiconductor device of claim 1 , wherein the portion of each of the vias comprising the conductive backfill material have diameters matching the rest of each of said vias.
5 . The semiconductor device of claim 1 , wherein the backfill material and the conductive material are the same.
6 . The semiconductor device of claim 1 , wherein the group of one or more semiconductor dies comprises a first group of one or more semiconductor dies, the memory die comprises a first memory die, the semiconductor device further comprising:
a third major planar surface,
a fourth major planar surface,
a second set of vias exposed at the fourth major planar surface, each via of the second set of vias comprising a conductive material and having a concave meniscus at the fourth major planar surface; and
conductive backfill material backfilling the concave meniscus in said each via of the second set of vias, the backfill material bringing each said via of the second set of vias flush with the fourth major planar surface.
7 . The semiconductor device of claim 6 , wherein the first and second groups of one or more semiconductor dies are physically and electrically coupled to each other at the second and third major planar surfaces.
8 . The semiconductor device of claim 6 , wherein the second and third major planar surfaces comprise bump pads, the bump pads of the second and third surfaces electrically and physically coupled to each other to bond the first and second groups of one or more semiconductor dies.
9 . The semiconductor device of claim 8 , wherein portions of the first set of vias comprising the conductive backfill material have enlarged diameters relative to the rest of the vias in the first set, and wherein portions of the second set of vias comprising the conductive backfill material have enlarged diameters relative to the rest of the vias in the second set.
10 . The semiconductor device of claim 8 , wherein portions of the first set of vias comprising the conductive backfill material have an enlarged diameter relative to the rest of the vias in the first set, and wherein portions of the second set of vias comprising the conductive backfill material have a trapezoid shape narrowing toward the fourth major planar surface.
11 . The semiconductor device of claim 8 , wherein portions of the first set of vias comprising the conductive backfill material have a trapezoid shape narrowing toward the first major planar surface, and wherein portions of the second set of vias comprising the conductive backfill material have a trapezoid shape narrowing toward the fourth major planar surface.
12 . A mirrored die pair (mDiP) semiconductor device, comprising:
a first group of semiconductor dies, the first group of semiconductor dies comprising:
a first memory die,
a first CMOS logic circuit die bonded to the first memory die,
a first major planar surface,
a second major planar surface opposite the first major planar surface,
a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface; and
conductive backfill material backfilling the concave meniscus in said each via of the first set of vias, the backfill material bringing each said via of the first set of vias flush with the first major planar surface; and
a second group of semiconductor dies bonded to the first group of semiconductor dies, the second group of semiconductor dies comprising:
a second memory die,
a second CMOS logic circuit die bonded to the second memory die,
a third major planar surface, and
a fourth major planar surface opposite the third major planar surface.
13 . The mDiP semiconductor device of claim 12 , wherein the portion of each of the vias in the first set of vias comprising the conductive backfill material have enlarged diameters relative to the rest of each of said vias in the first set of vias.
14 . The mDiP semiconductor device of claim 12 , wherein the portion of each of the vias in the first set of vias comprising the conductive backfill material have a trapezoid shape narrowing toward the first major planar surface.
15 . The mDiP semiconductor device of claim 12 , wherein the portion of each of the vias in the first set of vias comprising the conductive backfill material have diameters matching diameters of the conductive material in each of said vias in the first set of vias.
16 . The mDiP semiconductor device of claim 12 , wherein the backfill material and the conductive material are the same.
17 . The mDiP semiconductor device of claim 12 , the second set of semiconductor dies further comprising:
a second set of vias exposed at the fourth major planar surface, each via of the second set of vias comprising a conductive material and having a concave meniscus at the fourth major planar surface, and
conductive backfill material backfilling the concave meniscus in said each via of the second set of vias, the backfill material bringing each said via of the second set of vias flush with the fourth major planar surface.
18 . The mDiP semiconductor device of claim 17 , wherein the first and second groups of semiconductor dies are physically and electrically coupled to each other at the second and third surfaces, face to face.
19 . The mDiP semiconductor device of claim 10 , wherein portions of the first and second sets of vias comprising the conductive backfill material both have enlarged diameters relative to the rest of the first and second sets of vias, the enlarged diameter vias enhancing an electrical connection between said mDiP semiconductor devices in a stack of said mDiP semiconductor devices.
20 . A semiconductor device, comprising:
a group of one or more semiconductor dies, the first group of one or more semiconductor dies comprising:
a memory die,
a first major planar surface,
a second major planar surface,
a first set of vias exposed at the first major planar surface, each via of the first set of vias comprising a conductive material and having a concave meniscus at the first major planar surface; and
conductive backfill means for backfilling the concave meniscus in said each via and for bringing each said via flush with the first major planar surface.