LOW STRESS ASYMMETRIC DUAL SIDE MODULE
Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
1 . A semiconductor package comprising:
a lead frame directly coupled to and between a first substrate and a second substrate;
a first die coupled to the first substrate;
a second die coupled to the second substrate;
a first clip coupled to the first die; and
a second clip coupled to the second die.
2 . The semiconductor package of claim 1 , wherein the first clip is directly coupled to the first substrate and the second clip is directly coupled to the second substrate.
3 . The semiconductor package of claim 1 , further comprising a heat sink coupled with one of the first substrate, the second substrate, or any combination thereof.
4 . The semiconductor package of claim 1 , wherein the lead frame comprises one or more leads with a cross sectional shape that provides separation between the first substrate and the second substrate.
5 . The semiconductor package of claim 4 , wherein the cross sectional shape comprises a C-shape.
6 . The semiconductor package of claim 4 . wherein the cross sectional shape comprises an S-shape.
7 . A semiconductor package comprising:
a lead frame;
a first substrate mechanically and electrically coupled to one or more leads at a first side of the lead frame;
a second substrate mechanically and electrically coupled to one or more leads at a second side of the lead frame;
a first die coupled to the first substrate;
a second die coupled to the second substrate;
a first clip coupled to the first die; and
a second clip coupled to the second die;
wherein, the lead frame is directly coupled to the first substrate and the second substrate; and
wherein an end of a lead of the one or more leads comprises one or more bends configured to provide space between the first substrate and the second substrate.
8 . The semiconductor package of claim 7 , further comprising a third die coupled to the first substrate, a fourth die coupled to the second substrate, a third clip coupled to the third die, and a fourth clip coupled to the fourth die.
9 . The semiconductor package of claim 7 , wherein the first clip is directly coupled to the first die and is directly coupled to the first substrate.
10 . The semiconductor package of claim 7 , wherein the first substrate and the second substrate are asymmetrically coupled through the lead frame.
11 . The semiconductor package of claim 7 , wherein the end of the lead comprises a C-shaped bend.
12 . The semiconductor package of claim 9 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is aligned with the terminal of the second substrate.
13 . The semiconductor package of claim 9 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is misaligned with the terminal of the second substrate.
14 . The semiconductor package of claim 7 , wherein the end of the lead comprises an S-shaped bend.
15 . A semiconductor package comprising:
one or more leads directly coupled to and between a first substrate and a second substrate;
a first die coupled to the first substrate;
a second die coupled to the second substrate;
a first clip coupled to the first die; and
a second clip coupled to the second die;
wherein an end of a lead of the one or more leads comprises one or more bends configured to provide space between the first substrate and the second substrate.
16 . The semiconductor package of claim 15 , further comprising a heat sink coupled with one of the first substrate, the second substrate, or any combination thereof.
17 . The semiconductor package of claim 15 , wherein the first die is coupled between the first substrate and the first clip and the second die is coupled between the second substrate and the second clip.
18 . The semiconductor package of claim 15 , wherein the end of the lead comprises an S-shaped bend.
19 . The semiconductor package of claim 15 , wherein the end of the lead comprises a C-shaped bend.
20 . The semiconductor package of claim 15 , wherein the first substrate and the second substrate are exposed on an outer surface of the semiconductor package.