"inventor Kin-Hooi Dia" — IP Library Search

← Prev Next →

METHOD FOR BACKEND PHYSICAL DESIGN AND CIRCUIT LAYOUT

App. 19/449,454 Filed 2026-01-15 Docketed New Case - Ready for Examination

Patent Order

FRONT-END-OF-LINE FLOORPLAN OF INTEGRATED CIRCUIT THAT HAS DUMMIES INSERTED BY BLOCKAGE-AIDED DUMMY INSERTION AND RELATED METHOD

App. 19/380,978 Filed 2025-11-06 Docketed New Case - Ready for Examination

Patent Order

METHOD FOR PERFORMING DIGITAL OPERATIONS WITH AID OF FULL ADDER ARCHITECTURE WITH INPUT/OUTPUT POLARITY INVERSION, AND ASSOCIATED APPARATUS

App. 19/372,306 Filed 2025-10-29 Docketed New Case - Ready for Examination

Patent Order

PHYSICAL-AWARE DE-RATING METHOD FOR ADVANCED PROCESS LAYOUT EFFECT

App. 19/336,471 Filed 2025-09-22 Docketed New Case - Ready for Examination

Patent Order

Metal Density Control For Resistance Reduction For Back End Of Line Dummy Insertion By Adding Back End Of Line Blockage Guide Around Critical Path

App. 63/745,390 Filed 2025-01-15 Provisional Application Expired

Patent Order

Physical-Aware Derating Methods for Advanced Process Layout Effect

App. 63/741,996 Filed 2025-01-06 Provisional Application Expired

Patent Order

LOGIC CELL WITH SMALL CELL DELAY

App. 19/009,302 Filed 2025-01-03 Docketed New Case - Ready for Examination

Patent Order

Minimum Width Of Non-rectangle Shape Empty Region For Front-end-of-line Dummy Insertion By Adding Front-end-of-line Blockage

App. 63/717,829 Filed 2024-11-07 Provisional Application Expired

Patent Order

Low Power Adder and Multiplier Circuit

App. 63/714,171 Filed 2024-10-31 Provisional Application Expired

Patent Order

STANDARD CELL TOPOLOGY WITH POWER/PERFORMANCE/AREA OPTIMIZATION

App. 18/732,655 Filed 2024-06-04 Docketed New Case - Ready for Examination

Patent Order

Inventor — page 1 of 3 ← Prev Next →